This is an innovative practice Full Paper. Two of the seven ABET student learning outcomes (SLOs) require students have the ability to make informed judgements (SLO 4) or produce solutions (SLO 2) with consideration of global, economic, societal and environmental factors. Many engineering programs often meet these ABET outcomes through providing specifically tailored courses (such as a first-year and/or senior design experience) that address engineering design in a broader context. While these approaches can be effective, there is a need to infuse engineering design in a broader context throughout the existing discipline specific curriculum. This paper provides two examples of activities (a life cycle analysis lab and an inclusive design reflection) that help students put engineering design in a broader context in two existing sophomore level ECE courses. It is our hope that this paper will give electrical and computer engineering faculty (and engineering faculty in general) concrete ideas on how to infuse engineering design into a broader context in their existing technical coursework.

This Innovative Practice Work in Progress presents a step toward using virtual reality technology in the undergraduate electrical engineering classroom to offer remote students and students with disabilities access to ‘hands-on’ engineering labs. In this paper, we describe the VR pilot labs created for our freshman-level electronic circuits course and present initial feedback from students concerning the effectiveness of the VR environment for learning their way around a basic electronic circuits laboratory.

This is an innovative practice Full Paper. The COVID-19 pandemic forced virtually all education to operate remotely and faculty and students not typically accustomed to an online format had to quickly come up to speed in learning best-practices to teach and learn online. Engineering education research in the early days of the pandemic quickly revealed that building community and promoting inclusion in the classroom were key to promoting student success. However, in an emergency remote teaching environment where students are spread out and isolated from each other, building community can be more challenging. This paper studies student preferences (through student survey feedback) on community building and inclusion techniques by comparing three instructors' use of different techniques when teaching a common undergraduate engineering course.

This research full paper explores the magnitude of added course fees and miscellaneous costs in an engineering program and how these fees impact lower socio-economic students. Previous work has examined the effects of added course fees and development boards on students from various socioeconomic backgrounds. While the study found that students of varying socioeconomic status did not agree that they felt "ostracized" as a result of added course expenses, the study did not examine whether students felt other, less severe feelings of exclusion or loss of identity in relation to engineering costs.This paper provides an in-depth exploration of the effects of added course expenses on students' sense of inclusion in Electrical and Computer Engineering Programs. Specific emphasis is placed on how student experience varies by socio-economic status, and the experience of low-socio-economic status is treated with particular interest. "Added course expenses" includes any development boards, parts, and personal computing resources (laptops) necessary for student success but not directly charged by the school for enrollment in a course.

This abstract is for a Full Paper in the category of Innovative Practice. In Electrical and Computer Engineering programs, we are increasingly seeing a digital divide between students who can study and work on assignments 24/7 from powerful laptops, and those students who are forced to rely on the college's fixed, limited access computer labs to succeed. This paper discusses a proposal to address this problem in a low-to-no cost way at California Polytechnic State University by issuing underprivileged students laptops that have been recently retired from faculty use. The paper looks at the cost implications (and opportunities) of performing a light refurbishment on old faculty units, and provides benchmarks of retired faculty machines against newer faculty laptops across a number of common Electrical Engineering computation tasks.

This Research Paper examines the question of whether fixed computer labs are still a necessary or important facet of the Electrical Engineering Laboratory Environment. Large academic computer labs stocked with high performance computing workstations have long been a major feature of Electrical and Computer Engineering programs. Historically they have been used throughout the curriculum for everything from running complex image processing algorithms in Matlab to simulating and synthesizing advanced digital designs with CAD tools like Vivado. As the cost of computation has declined, however, and as students increasingly bring their own high performance computing devices to the lab, it is no longer clear that workstation-based computer labs provide a significant benefit for student learning. This paper explores this topic by looking at student in-lab computer usage patterns and preferences for an introductory digital design course at California Polytechnic State University San Luis Obispo. Our research also quantifies the potential environmental savings institutions can achieve by moving away from workstation-based labs by comparing average energy usage from students using lab computers versus those using their own laptops.

This Research Work-In-Progress Paper explores potential causes of measured differences in mental health between students in a joint Computer Engineering Program and students in the two home departments (Electrical Engineering and Computer Science). California Polytechnic State University (Cal Poly) currently runs its Computer Engineering Program (CPE) as a joint offering of the Electrical Engineering (EE) and Computer Science and Software Engineering (CSSE) Departments. The curriculum for this program is made up of roughly 50% computer science courses and 50% electrical engineering courses. With the exception of a single senior level capstone course, all CPE courses are also available to (and in many cases required for) students from the two home departments. As a result of this blended curriculum, it has long been assumed that CPE students would have a similar experience and a similar level of mental wellness to their peers in EE and CSSE. A recent study conducted at Cal Poly, however, indicates that CPE students are substantially more likely to screen positive for risk of Serious Mental Illness (SMI) than their peers. This study uses qualitative interviews with CPE, EE, and CSSE students try to determine potential stressors unique to each program. This study also delves into the quantitative survey data to look for population specific trends that may be feeding into this result.

Advances in technology have created unique opportunities for teaching digital design courses. Students in such courses no longer need to be present in the laboratory in order to obtain practical hands on experience and master the course material as students can complete laboratory assignments at home using relatively inexpensive commercial off-the-shelf development platforms and free software design tools. This paper describes an experience with porting and teaching a hardware-based digital design course to a 100% online course. Assessment data indicate that students who took the course online performed at least as well students in the traditional face-to-face course. We conclude that a fully-online hardware digital design course creates new and effective opportunities for students around the globe to obtain access to a hands-on engineering education.

Educational research has shown that students learn with deeper understanding and retain that understanding for a greater duration when they learn in an environment of inquiry. In order to foster an environment of inquiry in an embedded systems course, we have redesigned the course to give students more and more autonomy with course material as the course progresses. In this paper, we describe the design and preliminary assessment of a semi-autonomous embedded systems course in the computer engineering program at Cal Poly, San Luis Obispo. Preliminary assessment data indicate that the course appears to provide an environment of inquiry for students, but further assessment is required to determine if the semi-autonomous nature of the course increased student understanding and retention of course material.

This paper presents a hardware architecture for increased performance of color classification. In our architecture, color classification, based on an AdaBoost algorithm, identifies a pixel as having the color of interest or not. We designed the proposed architecture using Verilog HDL and implemented the design in a Xilinx Virtex-5 FPGA. The architecture for color classification can have 598 times performance improvement over an equivalent software solution and 1.9 times performance improvement over the leading hardware color classifier.

Matrix inversion is a common function found in many algorithms used in wireless communication systems. As FPGAs become an increasingly attractive platform for wireless communication, it is important to understand the trade-offs in designing a matrix inversion core on an FPGA. This article describes a matrix inversion core generator tool, GUSTO, that we developed to ease the design space exploration across different matrix inversion architectures. GUSTO is the first tool of its kind to provide automatic generation of a variety of general-purpose matrix inversion architectures with different parameterization options. GUSTO also provides an optimized application-specific architecture with an average of 59% area decrease and 3X throughput increase over its general-purpose architecture. The optimized architectures generated by GUSTO provide comparable results to published matrix inversion architecture implementations, but offer the advantage of providing the designer the ability to study the trade-offs between architectures with different design parameters.

This paper presents a parallelized architecture of multiple classifiers for face detection based on the Viola and Jones object detection method. This method makes use of the AdaBoost algorithm which identifies a sequence of Haar classifiers that indicate the presence of a face. We describe the hardware design techniques including image scaling, integral image generation, pipelined processing of classifiers, and parallel processing of multiple classifiers to accelerate the processing speed of the face detection system. Also we discuss the parallelized architecture which can be scalable for configurable device with variable resources. We implement the proposed architecture in Verilog HDL on a Xilinx Virtex-5 FPGA and show the parallelized architecture of multiple classifiers can have 3.3times performance gain over the architecture of a single classifier and an 84times performance gain over an equivalent software solution.

Small, dense underwater sensor networks have the potential to greatly improve undersea environmental and structural monitoring. However, few sensor nets exist because commercially available underwater acoustic modems are too costly and energy inefficient to be practical for this applications. Therefore, when designing an acoustic modem for sensor networks, the designer must optimize for low cost and low energy consumption at every level, from the analog electronics, to the signal processing scheme, to the hardware platform. In this paper we focus on the design choice of hardware platform: digital signal processors, microcontrollers, or reconfigurable hardware, to optimize for energy efficiency while keeping costs low. We implement one algorithm used in an acoustic modem design - Matching Pursuits for channel estimation - on all three platforms and perform a design space exploration to compare the timing, power and energy consumption of each implementation. We show that the reconfigurable hardware implementation can provide a maximum of 210X and 52X decrease in energy consumption over the microcontroller and DSP implementations respectively.

Matrix decomposition is required in various algorithms used in wireless communication applications. FPGAs strike a balance between ASICs and DSPs, as they have the programmability of software with performance capacity approaching that of a custom hardware implementation. However, FPGA architectures require designers to make a countless number of system, architectural and logic design decisions. By performing design space exploration, a designer can find the optimal device for a specific application, however very few tools exist which can accomplish this task. This paper presents automatic generation and optimization of decomposition methods using a core generator tool, GUSTO, that we developed to enable easy design space exploration with different parameterization options such as resource allocation, bit widths of the data, number of functional units and organization of controllers and interconnects. We present a detailed study of area and throughput tradeoffs of matrix decomposition architectures using different parameterizations.

Matrix inversion is an essential computation for various algorithms which are employed in multi-antenna wireless communication systems. FPGAs are ideal platforms for wireless communication; however, the need for vast amounts of customization throughout the design process of a matrix inversion core can overwhelm the designer. Decomposition methods provide the analytic simplicity and computational convenience necessary for computationally intensive matrix inversion. This paper presents automatic generation of different decomposition based matrix inversion architectures using a matrix inversion core generator tool, GUSTO with different parameterization options. We present automatic generation of a variety of general purpose matrix inversion architectures which have comparable results to published matrix inversion architecture implementations, but offer the advantage of providing the designer the ability to study the tradeoffs between architectures with different design parameters.