The authors present a statistics-based blind calibration technique for nonlinear memory errors in amplifier-sharing pipelined ADCs. The proposed method is fully digital and simple to implement. It detects memory errors in normal operation without system suspension for calibration. No special calibration signal or analog circuitry is necessary. Algorithm description and simulation results are presented. The proposed technique improves the power efficiency of pipelined ADCs by enabling sharing of low-gain operational amplifiers.

A practical approach for the compact modeling of electrostatic discharge (ESD) protection devices, using the behavioral language Verilog-A, is presented. Models of the NMOS transistor, the vertical n-p-n transistor, the diode, and the resistor have been developed, suitable for circuit-level simulation. Large-signal and small-signal models are provided for transient and alternating current (ac) simulation, respectively. A self-heating model is included for accurate simulation of the device ON-resistance under transient high-current conditions.