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Nicolas Coste

dblp:32/5212 · DBLP profile ↗
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3ranked-venue papers
3as first author
0since 2021 · last 2010
0000-0001-5234-2115ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 3 · 3 first-authorSystems, architecture and hardware · 1 · 1 first-authorTheory of computation · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 39% Electronic design automation · 30% Integrated circuit design · 30%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › asynchronous circuit design
globally asynchronous locally synchronous design		 0.112009
Towards Performance Prediction of Compositional Models in Industrial GALS Designs · CAV 2009
Electronic design automation › hardware verification and test
hardware verification		 0.112009
Towards Performance Prediction of Compositional Models in Industrial GALS Designs · CAV 2009
Performance modeling and evaluation
performance prediction		 0.112009
Towards Performance Prediction of Compositional Models in Industrial GALS Designs · CAV 2009
Performance modeling and evaluation
simulation		 0.012009
Towards Performance Prediction of Compositional Models in Industrial GALS Designs · CAV 2009
YearPublicationVenuePosition
2010 Ten Years of Performance Evaluation for Concurrent Systems Using CADP
Nicolas Coste, Hubert Garavel, Holger Hermanns, Frédéric Lang, Radu Mateescu 0001, Wendelin Serwe
 ISoLA (2)1
2009 Towards Performance Prediction of Compositional Models in Industrial GALS Designs
Nicolas Coste, Holger Hermanns, Etienne Lantreibecq, Wendelin Serwe
 CAV1
2008 Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures
abstract
As levels of parallelism are becoming increasingly complex in multiprocessor architectures GALS and asynchronous circuits, methodologies and software tools are needed to verify their functional behavior (qualitative properties) and to predict their performance (quantitative properties). This paper presents the work currently done in the multival project (pole de competitivite mondial Minalogic), in which verification and performance evaluation tools developed at INRIA and Saarland University are applied to three industrial architectures designed by Bull CEA/Leti and STMicroelectronics.
Nicolas Coste, Hubert Garavel, Holger Hermanns, Richard Hersemeule, Yvain Thonnart, Meriem Zidouni
 DATE1