Internet of Things (IoT) (or edge) devices are typically resource-constrained in terms of CPU, memory, and storage. Thus, it is viable for the devices to request resource provisioning to an edge server in the presence of growing data and heavy computation, as the edge server provides better accessibility than cloud servers. Consequently, the edge devices often perform computation and storage provisioning to the edge servers in large-scale data operations. However, the conventional methods for provisioning edge devices take into little consideration the characteristics of resources that jobs executed at the devices rely on. In particular, fully migrating computation jobs from the device to the server may waste valuable resources of the server without considering the computation and I/O characteristics of the jobs, thereby making the devices' resources idle. To overcome these limitations, we propose a novel Kubernetes-based resource augmentation framework, termed K-RAF, for provisioning edge devices with limited capabilities and accelerating the devices' job processing. Our experiment demonstrates that utilizing GPU acceleration, on average, K-RAF can run tasks 306 times faster than local computation on an edge device. Also, we show that utilizing the task distribution between an edge device and K-RAF can offer an average speedup of about 40% compared to K-RAF alone.

In cloud environments, GPU-based deep neural network (DNN) inference servers are required to meet the Service Level Objective (SLO) latency for each workload under a specified request rate, while also minimizing GPU resource consumption. However, previous studies have not fully achieved this objective. In this paper, we propose ParvaGPU, a technology that facilitates spatial GPU sharing for large-scale DNN inference in cloud computing. ParvaGPU integrates NVIDIA’s Multi-Instance GPU (MIG) and Multi-Process Service (MPS) technologies to enhance GPU utilization, with the goal of meeting the diverse SLOs of each workload and reducing overall GPU usage. Specifically, ParvaGPU addresses the challenges of minimizing underutilization within allocated GPU space partitions and external fragmentation in combined MIG and MPS environments. We conducted our assessment on multiple A100 GPUs, evaluating 11 diverse DNN workloads with varying SLOs. Our evaluation revealed no SLO violations and a significant reduction in GPU usage compared to state-of-the-art frameworks.

Industrial Internet of Things (IIoT) applications can greatly benefit from leveraging edge computing. For instance, applications relying on deep neural network (DNN) models can be sliced and distributed across IIoT devices and the network edge to reduce inference latency. However, low network performance between IIoT devices and the edge often becomes a bottleneck. In this study, we propose ScissionLite, a holistic framework designed to accelerate distributed DNN inference using lightweight data compression. Our compression method features a novel lightweight down/upsampling network tailored for performance-limited IIoT devices, which is inserted at the slicing point of a DNN model to reduce outbound network traffic without causing a significant drop in accuracy. In addition, we have developed a benchmarking tool to accurately identify the optimal slicing point of the DNN for the best inference latency. ScissionLite improves inference latency by up to 15.7× with minimal accuracy degradation.

This paper presents a virtualization-based computing and storage resource provisioning manager, termed RPM, for edge devices. Given a request from an edge device, RPM can perform dynamic volume provisioning and accelerated computation on augmented computing resources. Also, RPM can migrate application execution conducted by edge devices online. We show that RPM is a promising approach through our experiments.

Unlike database tables, B+-tree indexes are hierarchical and their structures change over time by node splitting operations, which may propagate changes from one node to another. The node splitting operation is difficult for the basic In-Page Logging (IPL) scheme to deal with, because it involves more than one node that may be stored separately in different flash blocks. In this paper, we propose Dynamic IPL B+-tree (d-IPL B+-tree in short) as a variant of the IPL scheme tailored for flash-based B+-tree indexes. The d-IPL B+-tree addresses the problem of frequent log overflow by allocating a log area in a flash block dynamically. It also avoids a page evaporation problem, imposed by the contemporary NAND flash chips, by introducing ghost nodes to d-IPL B+-tree. This simple but elegant design of the d-IPL B+-tree provides significant performance improvement over existing approaches. For a random insertion workload, the d-IPL B+-tree outperformed a B+-tree with the plain IPL scheme by more than a factor of two in terms of page write and block erase operations.

Flash memory has many advantages such as high performance, low electronic power, non-volatile storage and physical stability, over hard-disks. For this reason, flash memory has been deployed as data storage for mobile devices, including PDAs, MP3 players, laptop-computers and database systems. According to the cell type, flash memory can be divided into SLC(Single Level Chip) and MLC(Multi Level Chip). In general, SLC is known to have high performance and longer lifetime (i.e. more than 100 K wear-leveling) while MLC is to offer larger capacity and with low price but have wear leveling of not longer than 10 K. In this paper, we show that it is possible to design a fast and cost-efficient storage by combining two types of flash memories in a hybrid fashion. Specifically, we propose a hybrid flash memory solid state disk(SSD) scheme using FAST FTL for enterprise applications, where SLC chip is used as the log space for FAST while MLC chips store the normal data blocks. SLC chips allow fast and durable performance for write while MLC chips provide the large capacity. And, this is mainly due to the FAST FTL algorithm's characteristics: it tends to direct the random writes to SLC chips and direct the other most random read to MLC chips. By taking the advantages of both chip types, we can find an economically desirable flash SSD design option. Experimental results show that our hybrid flash SSD scheme outperforms MLC-only flash scheme by far both in terms of performance and price.

This paper presents Dynamic IPL B+-tree (d-IPL in short) as a B+-tree index variant for flash-based storage systems. The d-IPL B+-tree adopts a dynamic In-Page Logging (IPL) scheme in order to address a few new problems that are caused by the unique characteristics of B+-tree indexes The d-IPL B+-tree avoids the frequent log overflow problem by allocating a log area in a flash block dynamically. It also addresses elegantly the problem of page evaporation, imposed by the contemporary NAND flash chips, by introducing ghost nodes within the context of the dynamic IPL scheme. This simple but elegant design of the d-IPL B+-tree improves the performance significantly. For a random insertion workload, the d-IPL B+-tree index outperformed a B+-tree with a plain IPL scheme by more than a factor of two in terms of page write and block erase operations.

Recently, flash memory(in particular, NAND) is being rapidly deployed as data storage for mobile platforms such as PDAs, MP3 players, mobile phones and digital cameras, mainly because of its many advantages over its competitor, hard disk, including its low electronic power, non-volatile storage, high performance, physical stability, smaller size, light weight, and portability. Considering its rapid technical improvement both in capacity and speed, it will have a competitive advantage over its rivalry minidrive (i.e. a small size hard disk) under 100 Gbytes within a few years, As the applications in next generation mobile platforms become large, complex, and more data-oriented, they requires the database technology, because the file interface is too complex to manage their complicated data requirements. However, flash memory, compared to hard disk, has a few unique characteristics, and thus the traditional disk-based database technology does not seem to go well with flash memory. Therefore, we need to revisit almost every aspect of DBMS implementation techniques from the perspectives of flash memory. In this paper, we introduce the technical characteristics of flash memory, which we think might have huge impact on database performance to database community that are 1) no-overwrite (erase-before-write paradigm), 2) asymmetric read and write speed, and 3) no seek or rotation time. These small differences necessitate us to revisit all the major DBMS modules which have evolved over the several decades. Based on the characteristics, we identify several key issues in implementing major DBMS modules, and suggest alternative approaches to solve the issues. The topics covered in this article are neither comprehensive nor in-depth, but the main goal of this article is just to issue that a practical and urgent research topic is ahead and it poses us many challenges and opportunities.