In this paper, we present an error-driven adaptive sampling algorithm called adaptive grid refinement (AGR) algorithm to automatically generate performance macromodels for analog circuits. Starting from samples on a coarse grid, the AGR algorithm builds a global model and validates its accuracy on an independent validation data set sampled within this grid. If this model is not accurate enough on the validation data, the grid is split into equal sized smaller grids. On each of these grids, a local model is built using samples on this grid and its neighboring and validated similarly. A grid will not be further refined only if the corresponding local model is accurate on its validation data set. The algorithm will stop when all the local models are accurate on their corresponding validation data set. We build six performance macromodels of a CMOS opamp using the AGR algorithm and compare it with the competing techniques. The strengths and weaknesses of the proposed algorithm are discussed.

We propose an accuracy driven synthesis methodology for analog circuits. The proposed approach relies on macro-models for performance estimation and is thus orders of magnitude faster than simulation based synthesis techniques. Unlike existing macro-model based approaches, which use static models, our approach dynamically improves the accuracy of the model during synthesis to ensure true convergence. Our method is based on identifying and accurately modeling those regions in the design space where feasible designs lie. The identified feasible regions and their corresponding models are used in conjunction with an initially generated global model for performance estimation. Experimental results demonstrate that the proposed approach is able to synthesize designs using the enhanced performance models quickly, yet accurately.

Many approaches to analog performance parameter macro modeling have been investigated by the research community. These models are typically derived from discrete data obtained from circuit simulation using numerous input combinations of component sizes for a given circuit topology. The simulations are computationally intensive, therefore it is advantageous to reduce the number of simulations necessary to build an accurate macro model. We present a new algorithm for adaptively sampling multi-dimensional black box functions based on Duchon pseudo-cubic splines. The splines readily and accurately model high dimensional functions based on discrete unstructured data and require no tuning of parameters as seen in many other interpolation methods. The adaptive sampler, in conjunction with pseudo-cubic splines, is used to accurately model various analog performance parameters for an operational amplifier topology using fewer sample points than traditional gridded and quasi-random sampling methodologies.

Fast and accurate performance estimation methods are essential to automated synthesis of analog circuits. Development of analog performance models is difficult due to the highly nonlinear nature of various analog performance parameters. This paper presents a neural network-based methodology for creating fast and efficient models for estimating the performance parameters of CMOS operational amplifier topologies. Effective methods for generation and use of the training data are proposed to enhance the accuracy of the neural models. The efficiency and accuracy of the resulting performance models are demonstrated via their use in a genetic algorithm-based circuit synthesis system. The genetic synthesis tool optimizes a fitness function based on user-specified performance constraints. The performance parameters of the synthesized circuits are validated by SPICE simulations and compared with those predicted by the neural network models. Experimental studies demonstrate that neural network modeling is an effective, fast, and accurate methodology for performance estimation.