System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design-for-testability methodologies are usually required for testing different cores. Another issue is test integration. The purpose of this paper is to present a hierarchical test scheme for SOC with heterogeneous core test anti lest access methods. A hierarchical test manager (HTM) is proposed to generate the control signals for these cores, taking into account the IEEE P1500 Standard proposal. A standard memory BIST interface is also presented, linking the HTM and the memory BIST circuit. It can control the BIST circuit with the serial or parallel test access mechanism. The hierarchical test control scheme has low area anti pin overhead, and high flexibility. An industrial case using this scheme has been designed, showing an area overhead of only about 0.63%.

A layout style that enables either an automatic layout synthesizer or a layout designer to take full advantage of the second metal layer available from today's technology is proposed. The style not only facilitates power/ground diffusion overlapping but also simplifies the intracell routing problem by having power/ground in the middle and routing in the upper and the lower constraint-free regions. An automatic leaf cell layout synthesizer, called THEDA.P, that is based on the proposed style has been implement. Using the same transistor placement algorithm, THEDA.P outperforms a synthesizer based on T. Uehara and W.M. van Cleemput's (1981) approach by almost 20% in layout compactness across a wide range of small-scale integrated circuits. THEDA.P has been used to build a standard cell library that was previously handcrafted. Results from designing two modules show that THEDA.P's layout quality is very competitive.>

We propose a new layout style that enables an automatic layout synthesizer to take full advantage of the second metal layer available from today's technology.our style not only facilitates power/grotmd-diffttsion overlapping but also sirnplities the intra-cell routing problem.We have implemented an automatic layout synthesizer, called THEDA.P (Tsing Hua Electronic Design Automation), based on the proposed style.Using the same transistor placement algorithm, THEDA.P outperforms a synthesizer based on [Ueh8 1]'s style by almost 20% in layout mmpacmess across a wide range of SS1 circuits.THEDA.P has been used to build a standard cell library that was previously handcrafted.Results from designing two ASIC modules show that THEDA.P's layout quality is very competitive.

We propose a new approach for reducing the density of a channel by routing some nets (or subnets) over the cells (i.e.outside the channel).Previous research assumed that the more nets being routed over the cells the greater the reduction in the channel density.We show that only the removal of critical nets contributes to the reduction in the channel density.We divide channel into zones where each zone has a zone density and the removal of any net from a zone will reduce its density by one.In order to reduce the channel density, only certain critical zones need to have their nets routed over the cells.A bipwtite graph is used to represent the relationship between nets and zones.The problem is transformed into a constrained covering problem and formulated as an integer liiear programming problem.In comparison with previous research our approach reduces more channel densities while using fewer tracks over the cells.For Deutsch's difficult channel, previous approach needs 15 &acks over the cells to reduce the channel density by 3 while we need only 5 tracks to achieve the same result.

An automatic layout generation system, called LiB, for the small-scale integrated (SSI) cells used in CMOS VLSI design, is presented. LiB takes a transistor-level circuit schematic in SPICE format and outputs a mask layout in CIF. The layout style is a modification of that proposed by T. Uehara, and W. M. van Cleemput (IEEE Trans. Comput., vol.C-30, no.5, p.305-12, 1981). An optimal transistor chaining algorithm has been developed to derive a transistor placement with a minimum number of diffusion separations. To meet the cell height constraint, large transistors are folded into multiple columns algorithmically. The whole cell is divided into five routing regions. Two are on the diffusion island and the others are rectilinear-shaped routing channels. A graph-theoretic method for selecting nets (subnets) for routing on the diffusion island is proposed. A global routing algorithm has been developed to assign the remaining nets to the three rectilinear channels. For the detailed routing SILK, a simulated evolution router, is employed. LiB can be used as a cell library builder or as a subsystem of a random logic module generator. Users can alternate LiB's layout using a symbolic editor.>

An approach for reducing the density of a channel by routing some nets (or subnets) over the cells (i.e., outside the channel) is proposed. It is shown that only the removal of critical nets contributes to the reduction in the channel density. The channel is divided into zones, each having a zone density where the removal of any net from a zone will reduce its density by one. To reduce the channel density, only certain critical zones need to have their nets routed over the cells. A bipartite graph is used to represent the relationship between nets and zones. The problem is transformed into a constrained covering problem and formulated as an integer linear programming problem. Compared to previous research, the approach reduces more channel densities while using fewer tracks over the cells. For Deutsch's difficult channel, a previous approach needs 15 tracks over the cells to reduce the channel density by 3, whereas the present needs only 5 tracks to achieve the same result. >

We present an automatic layout generation system, called LiB, for the library cells used in CMOS ASIC design. LiB takes a transistor-level circuit schematic in SPICE format and outputs a symbolic layout. Our layout style is similar to that proposed by Uehara and van Cleemput in [17]. We propose several heuristic algorithms to solve the transistor-clustering, -pairing, -chaining, -folding, the chain placement, the routing, and the net assignment problems, respectively. Experimental results are presented to show the capability of LiB.

A fast algorithm is proposed for the transistor-chaining problem in CMOS functional cell layout based on the layout style of T. Uehara and W.M. van Cleemput (1981). The algorithm takes a transistor-level circuit schematic and outputs a minimum set of transistor chains. Possible diffusion abutments between the transistor pairs are modeled as a bipartite graph. A depth-first search algorithm is used to search for the optimal chaining. Theorems on the set of branches that needs to be explored at each node of the search tree are derived. A theoretical lower bound on the size of the chain set is also derived. This bound enables one to prune the search tree efficiently. The algorithm has been implemented and tested and is able to find optimal solutions almost instantly for all the cases from the literature that were examined.>

A fast algorithm is produced for the optimal transistor chaining problem in CMOS functional cell layout based on T. Uehara and W.M. van Cleemput's layout style (IEEE Trans. Comput., vol. C-30, p.305-12, May 1981). The algorithm takes a transistor-level circuit schematic and outputs a minimum set of chains. Possible diffusion abutments between the transistor pairs are modeled as a bipartite graph. A depth-first search algorithm is used to search for the optimal chaining. Theorems on the number of branches needed to be explored at each node of the search tree are derived. A theoretical lower bound on the size of the chain set is derived. This bound enables pruning the search tree efficiently. The algorithm has been implemented and tested. It is able to find optimal solutions almost instantly for all the cases available to use from the literature.>