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Sven Woop

dblp:32/6497 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 2014
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Graphics, computer vision, multimedia, augmented reality and games · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer graphics and multimedia
3 papers
Rendering · 100%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
GPUs and heterogeneous computing · 39% Processor architecture and microarchitecture · 31% Hardware accelerators and domain-specific architectures · 31%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Rendering
ray tracing
0.432014
Embree: a kernel framework for efficient CPU ray tracing · ACM Trans. Graph. 2014
Combining Single and Packet-Ray Tracing for Arbitrary Ray Distributions on the Intel MIC Architecture · IEEE Trans. Vis. Comput. Graph. 2012
RPU: a programmable ray processing unit for realtime ray tracing · ACM Trans. Graph. 2005
Rendering › ray tracing
real-time ray tracing
0.112005
RPU: a programmable ray processing unit for realtime ray tracing · ACM Trans. Graph. 2005
GPUs and heterogeneous computing › graphics accelerator
ray tracing hardware
0.112005
RPU: a programmable ray processing unit for realtime ray tracing · ACM Trans. Graph. 2005
Hardware accelerators and domain-specific architectures › many-core accelerator
Intel MIC architecture
0.012012
Combining Single and Packet-Ray Tracing for Arbitrary Ray Distributions on the Intel MIC Architecture · IEEE Trans. Vis. Comput. Graph. 2012
Processor architecture and microarchitecture
SIMD
0.012012
Combining Single and Packet-Ray Tracing for Arbitrary Ray Distributions on the Intel MIC Architecture · IEEE Trans. Vis. Comput. Graph. 2012

Methods — techniques the papers use, named apart from their topics

hybrid packet/single-ray tracing · 0.3bounding volume hierarchy · 0.3packet tracing · 0.2SIMD kernel design · 0.2FPGA prototype · 0.1
YearPublicationVenuePosition
2014 Embree: a kernel framework for efficient CPU ray tracing
abstract
We describe Embree, an open source ray tracing framework for x86 CPUs. Embree is explicitly designed to achieve high performance in professional rendering environments in which complex geometry and incoherent ray distributions are common. Embree consists of a set of low-level kernels that maximize utilization of modern CPU architectures, and an API which enables these kernels to be used in existing renderers with minimal programmer effort. In this paper, we describe the design goals and software architecture of Embree, and show that for secondary rays in particular, the performance of Embree is competitive with (and often higher than) existing state-of-the-art methods on CPUs and GPUs.
Ingo Wald, Sven Woop, Carsten Benthin, Gregory S. Johnson, Manfred Ernst
ACM Trans. Graph.2
2012 Combining Single and Packet-Ray Tracing for Arbitrary Ray Distributions on the Intel MIC Architecture
abstract
Wide-SIMD hardware is power and area efficient, but it is challenging to efficiently map ray tracing algorithms to such hardware especially when the rays are incoherent. The two most commonly used schemes are either packet tracing, or relying on a separate traversal stack for each SIMD lane. Both work great for coherent rays, but suffer when rays are incoherent: The former experiences a dramatic loss of SIMD utilization once rays diverge; the latter requires a large local storage, and generates multiple incoherent streams of memory accesses that present challenges for the memory system. In this paper, we introduce a single-ray tracing scheme for incoherent rays that uses just one traversal stack on 16-wide SIMD hardware. It uses a bounding-volume hierarchy with a branching factor of four as the acceleration structure, exploits four-wide SIMD in each box and primitive intersection test, and uses 16-wide SIMD by always performing four such node or primitive tests in parallel. We then extend this scheme to a hybrid tracing scheme that automatically adapts to varying ray coherence by starting out with a 16-wide packet scheme and switching to the new single-ray scheme as soon as rays diverge. We show that on the Intel Many Integrated Core architecture this hybrid scheme consistently, and over a wide range of scenes and ray distributions, outperforms both packet and single-ray tracing.
Carsten Benthin, Ingo Wald, Sven Woop, Manfred Ernst, William R. Mark
IEEE Trans. Vis. Comput. Graph.3
2005 RPU: a programmable ray processing unit for realtime ray tracing
abstract
Recursive ray tracing is a simple yet powerful and general approach for accurately computing global light transport and rendering high quality images. While recent algorithmic improvements and optimized parallel software implementations have increased ray tracing performance to realtime levels, no compact and programmable hardware solution has been available yet.This paper describes the architecture and a prototype implementation of a single chip, fully programmable Ray Processing Unit (RPU). It combines the flexibility of general purpose CPUs with the efficiency of current GPUs for data parallel computations. This design allows for realtime ray tracing of dynamic scenes with programmable material, geometry, and illumination shaders.Although, running at only 66 MHz the prototype FPGA implementation already renders images at up to 20 frames per second, which in many cases beats the performance of highly optimized software running on multi-GHz desktop CPUs. The performance and efficiency of the proposed architecture is analyzed using a variety of benchmark scenes.
Sven Woop, Jörg Schmittler, Philipp Slusallek
ACM Trans. Graph.1