Demo Data from VLDB 2026 / reviewers in the wild / expert
Elena Guralnik
dblp:32/7693
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 2011
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-authorTheory of computation · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test › test generation › functional test generation
constrained-random test generation |
0.1 | 1 | 2011 | Simulation-Based Verification of Floating-Point Division · IEEE Trans. Computers 2011 |
Electronic design automation
hardware verification and test |
0.1 | 1 | 2011 | Simulation-Based Verification of Floating-Point Division · IEEE Trans. Computers 2011 |
Electronic design automation › hardware verification and test › functional verification
simulation-based verification |
0.1 | 1 | 2011 | Simulation-Based Verification of Floating-Point Division · IEEE Trans. Computers 2011 |
Electronic design automation › hardware verification and test
test generation |
0.1 | 1 | 2011 | Simulation-Based Verification of Floating-Point Division · IEEE Trans. Computers 2011 |
Methods — techniques the papers use, named apart from their topics
divide-and-conquer · 0.1constraint solving · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2011 | Simulation-Based Verification of Floating-Point DivisionabstractFloating-point division is known to exhibit an exceptionally wide array of corner cases, making its verification a difficult challenge. Despite the remarkable advances in formal methods, the intricacies of this operation and its implementation often render these inapplicable. Simulation-based methods remain the primary means for verification of division. FPgen is a test generation framework targeted at the floating point datapath. It has been successfully used in the simulation-based verification of a variety of hardware designs. FPgen comprises a comprehensive test plan and a powerful test generator. A proper response to the difficulties posed by division constitutes a major part of FPgen's capabilities. We present an overview of the relevant verification tasks supplied with FPgen and the underlying algorithms used to target them. Elena Guralnik, Merav Aharoni, Ariel J. Birnbaum, Anatoly Koyfman |
IEEE Trans. Computers | 1 |
| 2009 | Implementation Specific Verification of Divide and Square Root InstructionsabstractFloating point operations such as divide and square root are typically implemented in microcode rather than dedicated logic. Bugs in these operations missed by generic black-box verification tools, were analyzed. This led to the conclusion that the corner cases, in addition to being implementation dependent, could not be characterized in terms of special input or output values in a straightforward manner. However, many of those cases can be easily generalized for many known implementations. The typical implementation uses a known iterative approximation algorithm, such as the Newton-Raphson method, to calculate the desired result; thus, it is sufficient to produce the corner cases associated with the specific algorithm. We investigated the following problem: given an iterative algorithm to compute a binary floating point operation, the iteration number, and an interval, find random inputs for the operation that, after the requested iteration, yield a relative error within the specified interval. This paper describes a method to solve this problem. This method was implemented in a floating-point test generator and is currently being used to verify the floating-point units of several processors. Elena Guralnik, Ariel J. Birnbaum, Anatoly Koyfman, Avi Kaplan |
IEEE Symposium on Computer Arithmetic | 1 |