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Seong-Lyong Gong

dblp:32/8198 · DBLP profile ↗
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4ranked-venue papers
3as first author
0since 2021 · last 2018
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Hardware reliability and fault tolerance · 84% Memory systems · 16%

Topics — the 9 heaviest of 11, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance › error-correcting codes for memory
DRAM error correction
0.832018
DUO: Exposing On-Chip Redundancy to Rank-Level ECC for High Reliability · HPCA 2018
Frugal ECC: efficient and versatile memory error protection through fine-grained compression · SC 2015
CLEAN-ECC: high reliability ECC for adaptive granularity memory system · MICRO 2015
Hardware reliability and fault tolerance › memory fault tolerance
DRAM fault tolerance
0.312018
DUO: Exposing On-Chip Redundancy to Rank-Level ECC for High Reliability · HPCA 2018
Hardware reliability and fault tolerance › error-correcting codes for memory
rank-level ECC
0.312018
DUO: Exposing On-Chip Redundancy to Rank-Level ECC for High Reliability · HPCA 2018
Hardware reliability and fault tolerance › error-correcting codes for memory
chipkill correct
0.212015
Frugal ECC: efficient and versatile memory error protection through fine-grained compression · SC 2015
Hardware reliability and fault tolerance › error correction
error-correcting codes
0.212015
Frugal ECC: efficient and versatile memory error protection through fine-grained compression · SC 2015
Memory systems
memory compression
0.212015
Frugal ECC: efficient and versatile memory error protection through fine-grained compression · SC 2015
Hardware reliability and fault tolerance
memory reliability
0.212015
CLEAN-ECC: high reliability ECC for adaptive granularity memory system · MICRO 2015
Hardware reliability and fault tolerance › error correction › error-correcting codes
in-DRAM ECC
0.112018
DUO: Exposing On-Chip Redundancy to Rank-Level ECC for High Reliability · HPCA 2018
Hardware reliability and fault tolerance
error-correcting codes for memory
0.112015
Frugal ECC: efficient and versatile memory error protection through fine-grained compression · SC 2015

Methods — techniques the papers use, named apart from their topics

secondary correction · 0.3ECC · 0.3fine-grained compression · 0.2coverage-oriented compression · 0.2access granularity enforcement · 0.2
YearPublicationVenuePosition
2018 DUO: Exposing On-Chip Redundancy to Rank-Level ECC for High Reliability
abstract
DRAM row and column sparing cannot efficiently tolerate the increasing inherent fault rate caused by continued process scaling. In-DRAM ECC (IECC), an appealing alternative to sparing, can resolve inherent faults without significant changes to DRAM, but it is inefficient for highly-reliable systems where rank-level ECC (RECC) is already used against operational faults. In addition, DRAM design in the near future (possibly as early as DDR5) may transfer data in longer bursts, which complicates high-reliability RECC due to fewer devices being used per rank and increased fault granularity. We propose dual use of on-chip redundancy (DUO), a mech- anism that bypasses the IECC module and transfers on-chip redundancy to be used directly for RECC. Due to its increased redundancy budget, DUO enables a strong and novel RECC for highly-reliable systems, called DUO SDDC. The long codewords of DUO SDDC provide fundamentally higher detection and correction capabilities, and several novel secondary-correction techniques integrate together to further expand its correction capability. According to our evaluation results, DUO shows performance degradation on par with or better than IECC (average 2–3%), while consuming less DRAM energy than IECC (average 4–14% overheads). DUO provides higher reliability than either IECC or the state-of-the-art ECC technique. We show the robust reliability of DUO SDDC by comparing it to other ECC schemes using two different inherent fault-error models.
Seong-Lyong Gong, Jungrae Kim, Sangkug Lym, Michael B. Sullivan 0001, Howard David, Mattan Erez
HPCA1
2015 CLEAN-ECC: high reliability ECC for adaptive granularity memory system
abstract
Adaptive-granularity memory architectures have been considered mainly because of main memory bottleneck and power efficiency. Meanwhile, highly reliable protection schemes are getting popular especially in large computing systems. Unfortunately, conventional ECC mechanisms including Chipkill require a large number of symbols to guarantee strong protection with acceptable overhead. We propose a novel memory protection scheme called CLEAN (Chipkill-LEvel reliable and Access granularity Negotiable), which enables us to balance the contradicting demands of fine-grained (FG) access and strong & efficient ECC. To close a potentially significant detection coverage gap due to CLEAN's detection mechanism coupled with permanent faults, we design a simple mechanism access granularity enforcement. By enforcing coarse-grained (CG) access, we can get only the advantage of higher protection comparable to Chipkill instead of achieving the adaptive access granularity together. CLEAN showed Chipkill level reliability as well as improvement in performance, system and memory power efficiency by up to 11.8%, 10.8% and 64.9% with mixes of SPEC2006 benchmarks.
Seong-Lyong Gong, Minsoo Rhu, Jungrae Kim, Jinsuk Chung, Mattan Erez
MICRO1
2015 Frugal ECC: efficient and versatile memory error protection through fine-grained compression
abstract
Because main memory is vulnerable to errors and failures, large-scale systems and critical servers utilize error checking and correcting (ECC) mechanisms to meet their reliability requirements. We propose a novel mechanism, Frugal ECC (FECC), that combines ECC with fine-grained compression to provide versatile protection that can be both stronger and lower overhead than current schemes, without sacrificing performance. FECC compresses main memory at cache-block granularity, using any left over space to store ECC information. Compressed data and its ECC information are then frequently read with a single access even without redundant memory chips; insufficiently compressed blocks require additional storage and accesses. As examples, we present chipkill-correct ECCs on a non-ECC DIMM with x4 chips and the first true chipkill-correct ECC for x8 devices using an ECC DIMM. FECC relies on a new Coverage-oriented-Compression that we developed specifically for the modest compression needs of ECC and for floating-point data.
Jungrae Kim, Michael B. Sullivan 0001, Seong-Lyong Gong, Mattan Erez
SC3
2009 Opportunistic Scheduling and Adaptive Modulation in Wireless Networks with Network Coding
abstract
So far, many researches on network coding are performed with higher layer protocols such as MAC, routing, and flow control protocols without consideration of physical layer issues such as channel conditions of links. However, in wireless networks, the consideration of properties at the physical layer is important to improve system performance. Hence, in this paper, we study an opportunistic scheduling and adaptive modulation problem for wireless networks with network coding, which is a joint problem for MAC and physical layers. A similar problem was studied in considering an idealized system in which the data rate of each link is modeled with the Shannon capacity. They showed that to maximize the throughput of a transmission, the optimal subset of native packets that are encoded within a coded packet should be selected based on the channel condition at the destination for each native packet. Moreover, they also showed that it may not be the optimal selection to encode all possible native packets within a coded packet. In this paper, we consider a more realistic model than that of with practical modulation schemes such as M-PSK and MQAM. We show that the optimal policy that maximizes the throughput of a transmission is to encode all available native packets within a coded packet regardless of the channel condition at the destination for each native packet, which is a different conclusion from that of. However, we show that adaptive modulation, in which its constellation size in a coded packet is adjusted based on the channel condition of each destination node, provides a higher throughput than the scheme with fixed modulation, in which its constellation size is always fixed regardless of the channel condition at each destination node.
Seong-Lyong Gong, Byung-Gook Kim, Jang-Won Lee 0001
VTC Spring1