In the era of big data, the demand for memory capacity in modern computing systems is surging. The CXL-SSD, NAND Flash-based memory expander using emerging Compute Express Link (CXL), has become a promising solution for efficient memory expansion. However, the memory-expansion scenario poses severe performance and endurance challenges for CXL-SSDs, and existing works fail to fully address them due to the usage of traditional SSDs as back-end media. To optimize these aspects, we propose LsCMM-H, a Total-Cost-of-Ownership (TCO) -efficient CXL-SSD architecture with Zoned Namespace (ZNS) SSDs as back-end media for better latency and lifetime. LsCMM-H employs hardware-software co-designed log management, low-overhead data-tiering-based garbage collection mechanism, and read acceleration to leverage the benefits of ZNS. Based on our evaluation, LsCMM-H reduces tail latency by 49.9%, improves throughput by 41.9%, endurance by 280.5%, and saves TCO by 72.4% compared to vanilla CXL-SSD. The additional comparison also demonstrates the superiority of our proposed log structure.

Neuromorphic computing has emerged as a revolutionary technology in consumer electronics, with computing-in-memory (CIM) attracting considerable attention for its potential to minimize data transfer. However, most CIM accelerators necessitate numerous digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) for mixed-signal data processing, resulting in substantial area and energy overheads. This study introduces a lightweight CIM accelerator, Light-CIM, which operates with fully analog tiles (FANTs) and employs a nonideality-aware algorithm. A FANT consists of one-transistor-one-resistor (1T1R) arrays based on resistive random access memory (RRAM) and customized analog peripheral circuits for data processing. The intratile data computation, transfer, and buffering are all in analog voltage, current, or RRAM resistance, thus eliminating costly DACs and ADCs for intermediate data conversions in conventional CIM accelerators. The fully analog approach significantly reduces power consumption attributed to ADCs, accounting for only 2.5% of the total power consumption. Additionally, a nonideality-aware training algorithm is employed to enhance the robustness of the hardware system. It models and incorporates nonidealities of circuits in software training, including read nonlinearities, mismatches, variations, and noises in the hardware analog data flow. Experimental results demonstrate that Light-CIM achieves accuracy close to software performance in various NN models. Light-CIM accomplishes a compute density of 3.91 TOPS/${\mathrm { mm}}^{2}$and an energy efficiency of 3.08 TOPS/W, both highly competitive compared to state-of-the-art works.

Computing-in-memory (CIM) based on embedded nonvolatile memory (NVM) realizes energy-efficient acceleration of convolution neural network (CNN) with less data movement and high computing parallelism. Because the deployment environments for edge devices are usually subject to changes, it is necessary for the CIM accelerators to support light-weight on-chip training with efficient implementation for environmental adaptation. However, previous CIM accelerators for edge devices mainly realize the inference while the training is performed on cloud. The limited endurance of NVMs hinders the CIM accelerators from supporting on-chip training that involves a large number of weight updates. In this paper, an endurance friendly CIM accelerator based on NVM, EF-CIM, is presented with bit-aware wear-leveling for efficient on-chip training in edge devices. Firstly, the bit split weight mapping (BSWM) splits the multi-bit weights into individual bits and stores them in the array alternately. Then, the bit-aware wear-leveling (BAWL) reduces the NVM updates by using verify write and block switch methods. An EF-CIM accelerator with BSWM and BAWL that is evaluated for 8-bit inputs and weights in the 28nm process achieves ~3.58/3.26 TOPS/W energy efficiency for feed-forward/ back-propagation, 5X lower computing latency. The BAWL also alleviates the wear of NVMs by 40X, achieving high NVM training reliability.

ReRAM has emerged as a promising candidate for computing-in-memory due to its excellent compatibility with advanced CMOS processes, high density, and non-volatility. Meanwhile, Digital Computing-in-Memory (DCIM) offers higher energy efficiency than its analog counterpart and supports full-precision processing. However, existing ReRAM-based DCIMs are hindered by error-prone readout and low input parallelism. The inefficient bit-width reconfiguration also incurs significant hardware overhead during neural network mapping. This paper reports a 64Kb DCIM engine based on 1T2R ReRAM bitcells for multiply-and-Accumulate(MAC) acceleration. The ternary-input Booth-assisted multiply-in-memory (TB-MIM) flow allows bi-state ReRAM with limited readout margin to achieve high-accuracy computation with high parallelism. The corresponding reconfigurable vector adder-tree and accumulator (ReV-A2) effectively facilitate practical hybrid-precision network mapping. Simulations show that the proposed DCIM engine achieves a normalized throughput rate of 284.44 GOPS/Kb and an energy efficiency of 730.16 TOPS/W, surpassing previous ReRAM-based DCIM designs by$3.3\times $.

In recent years, Ising machines have emerged as a promising hardware solution for tackling combinatorial optimization problems (COPs). However, existing Ising solvers, whether based on discrete-time or continuous-time approaches, often face challenges in balancing solution quality, scalability, and computational speed. Discrete-time solvers typically suffer from slow convergence due to the sequential nature of spin updates, while continuous-time solvers often lack effective annealing mechanisms, limiting their solution accuracy. To address these limitations, this work proposes a novel architecture that integrates a differential Resistive Random Access Memory (RRAM) cell-based Ising design with a Randomized Granular Update (RAGU) method. This approach enhances scalability to larger spin systems while maintaining robust performance against circuit non-idealities and device variations. Additionally, an adaptive bitline (BL) voltage clamper is incorporated into the read path to limit current magnitudes, significantly improving power efficiency. A key feature of the RAGU method is its ability to naturally introduce randomness during the update process through coarse-grained updates, serving as an imprecise but effective sampling mechanism. This innovation not only accelerates convergence and improves the system’s ability to escape local minima but also ensures high solution quality. Extensive simulations and experiments on randomly weighted graphs with varying densities demonstrate that the proposed architecture consistently achieves near-optimal solutions ($>$96%) while drastically reducing the time-to-solution to as low as 0.6$\mu$s.

Federated learning (FL), as a powerful learning paradigm, trains a shared model by aggregating model updates from distributed clients. However, the decoupling of model learning from local data makes FL highly vulnerable to backdoor attacks, where a single compromised client can poison the shared model. While recent progress has been made in backdoor detection, existing methods face challenges with detection accuracy and runtime effectiveness, particularly when dealing with complex model architectures. In this work, we propose a novel approach to detecting malicious clients in an accurate, stable, and efficient manner. Our method utilizes a sampling-based network representation method to quantify dissimilarities between clients, identifying model deviations caused by backdoor injections. We also propose an iterative algorithm to progressively detect and exclude malicious clients as outliers based on these dissimilarity measurements. Evaluations across a range of benchmark tasks demonstrate that our approach outperforms state-of-the-art methods in detection accuracy and defense effectiveness. When deployed for runtime protection, our approach effectively eliminates backdoor injections with marginal overheads.

Computing-in-memory (CIM) is a promising technique for hardware acceleration of neural networks (NNs) with high performance and efficiency. However, conventional dense mapping scheme cannot well support the compression and optimization of irregular sparse NNs. In this paper, we propose a heuristic and greedy weight remapping scheme for irregular sparse neural networks implemented on CIM accelerator in edge AI applications. The genetic algorithm (GA) is proposed for the first time to be utilized in the column shuffle for sparse weight remapping. Combined with the granularity exploration of the CIM, the proportion of the compressible all-zero rows increase remarkably. A greedy algorithm is then employed to planarize the unevenly compressed units, thus to improve the storage utilization of the crossbar. For hardware optimization, the pipeline is customized with a zero-skipping circuit to leverage the bit-level activation sparsity at runtime. Our results show that the proposed remapping scheme achieves 70%-94% utilization rate of the sparsity, and an average of $1.3 \times$ increment compared with the naive compression. The cooptimized CIM achieves $3-7.6 \times$ speedup and $2.1- 4.8 \times$ energy efficiency, compared with the baseline for dense NNs.

Neuromorphic computing approaches such as Spiking Neural Networks (SNN) have been increasingly adopted in bio-signal processing and interpretation due to its intrinsic neurodynamic attribute. Nevertheless, reconciling performance and power efficiency in SNN implementation is still a bottleneck. Single-spike neural coding scheme, which is an extremely sparse coding scheme, provides a solution to bridge the gap. In this work, a neuromorphic architecture, using binary single spike neural signals, is proposed with both algorithm and hardware implementation. A sparsity-aware spatial-temporal back-propagation training method is proposed together with a single-spike coding scheme. Also, a novel neuromorphic accelerator is co-designed with algorithmic optimization and implemented in 40nm CMOS process. Experimental results show that the proposed processor reaches an accuracy of 94.61% on the MNIST dataset, 93.59% on the N-MNIST dataset, and 93.27% on the ECG dataset, respectively, while consumes$0.173\mu\mathrm{J}$per ECG classification task and 0.16mm2on-chip area. The overall power consumption is reduced by 91.68% compared to the state-of-the-art systems.

Computing-in-memory (CIM) relieves the Von Neumann bottleneck by storing the weights of neural networks in memory arrays. However, two challenges still exist, hindering the efficient acceleration of convolutional neural networks (CNN) in artificial intelligence (AI) edge devices. Firstly, the activations for sliding window (SW) operations in CNN still bring high memory access pressure. This can be alleviated by increasing the SW parallelism, but simple array replication suffers from poor array utilization and large peripheral circuits overhead. Secondly, the partial sums from individual CIM arrays, which are usually accumulated to obtain the final sum, introduce large latency due to enormous shift-and-add operations. Moreover, high-resolution ADCs are also needed to reduce the quantization error of partial sums, further increasing the hardware costs. In this paper, a hardware-efficient CIM accelerator, ARBiS, is proposed with improved activation reusability and bit-scalable matrix-vector-multiplication (MVM) for CNN acceleration in AI edge applications. The cyclic-shift weight duplication exploits a third dimension of receptive field (RF) depth for SW weight mapping to reduce the memory accesses of activations, improving the array utilization. The parasitic-capacitance charge sharing is employed to realize high-precision analog MVM in order to reduce the ADC cost. Compared with conventional architectures, ARBiS with parallel processing of 9 SW operations achieves 56.6%~58.8% alleviation of memory access pressure. Meanwhile, ARBiS configured with 8-bit ADCs saves 92.53%~94.53% ADC energy consumption. An ARBiS accelerator is evaluated to realize a computational efficiency (CE) of 10.28 (10.43) TOPS/mm2, an energy efficiency (EE) of 91.19 (112.36) TOPS/W with 8-bit (4-bit) ADCs, achieving$11.4\sim 11.7\times $($11.6\sim 11.8\times $),$1.1\sim 3.3\times $($1.4\sim 4\times $) improvements over state-of-the-art works, respectively.

EMG based hand gesture recognition on convolutional neural networks (CNNs) has been widely learned, which gains high accuracy. However, CNN based systems are computationally complex and power consuming, thus hard to be deployed at edge. Biologically inspired, a new neuromorphic learning and computing approach for electromyogram (EMG) based hand gesture recognition tasks is proposed in this work. This approach designs an activate and inhibit joint processing spiking neural network (AIPS-SNN) which reaches an accuracy of 85.6% on Nina Pro dataset. Furthermore, the AIPS-SNN is deployed on the proposed memristor based computation in-memory (CIM) system, the power efficiency and area efficiency of which reach 10.146 TOPS/W and 35.399 GOPS/mm2, respectively. The experimental results indicate that the proposed neuromorphic CIM engine is promising for edge deployment.

Since deep learning was introduced into style transfer, remarkable results have been achieved in it and it is widely used in multimedia fields, such as photography. However, the computational costs of the existing state-of-the-art (SOTA) arbitrary style transfer algorithms are still too complex to apply them on mobile device and high resolution, and their performance on shape retention is not satisfactory enough. To deal with the above problems, we propose a novel arbitrary style transfer algorithm. Specially, we propose a new network which ensures the low computational cost and high shape retention. Moreover, we propose the weighted style loss function to improve the performance on style migration. The experimental results show that the proposed algorithm achieves better results with lower computational cost than the SOTA algorithms.

Finding enough accurate matching points is key for image stitching. However, the existing state-of-the-art algorithms fail to find enough accurate matching points when facing the challenge where detectable features are not obvious. In this paper, a novel algorithm called CNN-MP is proposed to directly obtain Matching Points between two images using the feature maps extracted by Convolution Neural Network (CNN) and CNN-MP skips the step of detecting keypoints. There are mainly five contributions in CNN-MP: 1) break the conventional image stitching steps without detecting keypoints; 2) a feature map calculation model is built to obtain matching points between the feature maps of two images; 3) establish a position model to map the obtained matching points to the original images; 4) the process of obtaining matching points is accelerated by dividing it into pre-locate and fine-locate; 5) establish the dataset to evaluate CNN-MP in the case where detectable features are not obvious. The experimental results show that the number of accurate matching points obtained by the proposed CNN-MP is at least 1.7 times that of the state-of-the-art algorithms: ORB, SIFT, LIFT and SuperPoint when facing the challenge where detectable features are not obvious. Moreover, CNN-MP also achieves good performance when the input images own significant detectable features.

This study proposed a novel nonvolatile static random access memory (nvSRAM) cell with two ferroelectric capacitors (FeCAPs) embedded inside a 4T SRAM cell, i.e., 4T2C, for minimal area penalty and full logic compatibility. The FeCAP with 10-nm-thick Hf0.5Zr0.5O2film shows excellent ferroelectricity (Pr = 15 μC/cm2) and good memory characteristics (cycles 1011). The 4T2C nvSRAM is capable of storing and restoring previous memory states for nonvolatile data storage. To compensate the leakage current in the dynamic nodes of 4T load less SRAM, we propose a dynamic current compensation operation scheme by exploiting the polarization-dependent leakage current of FeCAP. Outstanding characteristics were achieved in this nvSRAM cell: 1) elimination of the dc path; 2) ultralow store and restore power consumption; and 3) high area efficiency.

In this paper, an automated task partition method for multi-core system is proposed. To explore the full parallelism of an application written in sequential languages such as C/C++, we first present a coarse-grain intermediate representation called Function-ANd-Statement (FANS) which takes function call structure as well as statement structure into account. Based on the FANS intermediate representation, we propose a node fusion technique called Stratify And Grain-Controlled Fusion (SAGCF) to partition the whole application into many subtasks with the goal of maximizing parallelism in space and time dimensions as well as minimizing communication. All of these proposed techniques are implemented in an open source Automatic Task Partition Framework (ATPF). Finally, the feasibility of the proposed method is demonstrated by several cases.

A true random number generator using write speed variation of oxide-based RRAM is proposed for the first time. The signal of this physical unclonable function (PUF) is strong with long duration to be easily and accurately captured by simple circuit, of which the advantage is attributed to the mechanism that the speed variation amplifies the fluctuation of oxygen vacancy trap and de-trap. Some function parts of normal RRAM IP can be reused as entropy source cells and implementation circuit. The variation of write end point is monitored by a self-adaptive write drive circuit to trig a counter, and then serialized into a bit stream. The test chips, which are AlOx/WOx bilayer back-end RRAM fabricated in 0.18 Um logic process, passed all NIST tests with advantages of small area, low power, and not using post-processor corrector. Enough bits can be generated within the endurance limitation to ensure usual Internet of Things (IoT) security application.

An all-digital on-chip sensor using programmable ring oscillator (PRO) for advanced on chip variation (AOCV) characterization is proposed and verified in 28nm HKMG node. Bypassing technique combined with statistical testing based on array of PROs enables resolution of 1 pico-second. Multiple cells under test (CUTs) are embedded into one single PRO through programmability to get mask area cost effectiveness. Extra variation is eliminated by symmetrical duplicate structure. Test results indicate that there is a flex point around 7-stage on the curves of delay sigma/n vs. stage number. Local variation dominates and decreases significantly with the increase of stage number before 7-stage point. For small dimension, inverter is more sensitive to on-chip-variation than NAND. But no same trend is observed for large dimension. Curves of delay average vs. stage number and delay sigma/n vs. stage number among dies based on the same type of cell indicate a good uniformity.

Both 3D Vertical RRAM (VRRAM) and 3D Horizontal RRAM (HRRAM) architecture suffer from the issue of serious sneaking current, which leads to read or write disturbance and unacceptable power consumption waste, severely limiting its spatial stack-ability. In this work, the power consumption caused by sneaking current is separated out from the total set power consumption in HRRAM architecture. Then isolation cell structure is proposed to suppress the sneaking current. Simulation results show that total power consumption is reduced by about 30% with our proposed structure. Meanwhile, disturbance and read margin also show improvements.

Emerging nonvolatile memories (NVMs), such as MRAM, PRAM, and RRAM, have been widely investigated to replace SRAM as the configuration bits in field-programmable gate arrays (FPGAs) for high security and instant power ON. However, the variations inherent in NVMs and advanced logic process bring reliability issue to FPGAs. This brief introduces a low-power variation-tolerant nonvolatile lookup table (nvLUT) circuit to overcome the reliability issue. Because of large ROFF/RON, 1T1R RRAM cell provides sufficient sense margin as a configuration bit and a reference resistor. A single-stage sense amplifier with voltage clamp is employed to reduce the power and area without impairing the reliability. Matched reference path is proposed to reduce the parasitic RC mismatch for reliable sensing. Evaluation shows that 22% reduction in delay, 38% reduction in power, and the tolerance of variations of 2.5× typical RONor ROFFin reliability are achieved for proposed nvLUT with six inputs.

We propose co-optimization of VRRAM cell structure and array architecture as well as IR-drop-aware read/write algorithms to overcome issues of disturbance and IR drop from long wire. A bi-directional diode (2D) access device is combined with one resistor to form 2D1R cell. A dummy reference plane is inserted into array to set up the same IR drop path of reference cell with that of selected cell. Consequently, the same IR drop effect can be cancelled during read. The model for disturbance analysis is put forward. Voltage dropped on un-selected bit lines is the key parameter to suppress set disturbance. Set disturbance is significantly suppressed even when number of RRAM layers increases to 64. Set voltage has to meet corresponding requirements in order to minimize the disturbance risk.