Numerous threats are associated with the globalized integrated circuit (IC) supply chain, such as piracy, reverse engineering, overproduction, and malicious logic insertion. Many obfuscation approaches have been proposed to mitigate these threats by preventing an adversary from fully understanding the IC (or parts of it). The use of reconfigurable elements inside an IC is a known obfuscation technique, either as a coarse grain reconfigurable block (i.e., eFPGA) or as a fine grain element (i.e., FPGA-like look-up tables). This paper presents a security-aware CAD flow that is LUT-based yet still compatible with the standard cell based physical synthesis flow. More precisely, our CAD flow explores the FPGA-ASIC design space and produces heavily obfuscated designs where only small portions of the logic resemble an ASIC. Therefore, we term this specialized solution a “hybrid ASIC” (hASIC). Nevertheless, even for heavily LUT-dominated designs, our proposed decomposition and pin swapping algorithms allow for performance gains that enable performance levels that only ASICs would otherwise achieve. On the security side, we have developed novel template-based attacks and also applied existing attacks, both oracle-free and oracle-based. Our security analysis revealed that the obfuscation rate for an SHA-256 study case should be at least 45% for withstanding traditional attacks and at least 80% for withstanding template-based attacks. When the 80% obfuscated SHA-256 design is physically implemented, it achieves a remarkable frequency of 368MHz in a 65nm commercial technology, whereas its FPGA implementation (in a superior technology) achieves only 77MHz.

As CMOS technology continues to scale down due to advances in lithography, the interaction of neighboring patterns is exacerbated. Every pattern printed on silicon is influenced by its neighbors given a technology-specific interaction range. As transistors and cells shrink to sizes of the same order of the interaction range, pattern dependencies at the 16-nm node (and below) make the prediction of functional and parametric yield challenging. Precharacterizing all combinations of layouts as a function of all possible neighboring patterns is impractical due to exponential complexity, whereas silicon characterization of all patterns is practically impossible. In this paper, we propose a virtual characterization vehicle (VCV) methodology that can exhaustively identify all uniquely occurring layout patterns in a standard cell library. VCVs can expose all cell neighboring arrangements as a function of a radius of influence while compiling the pattern frequency and also uncovering the arrangement of cells that create unique patterns. Effects that span multiple layers are also captured in our analysis. VCV results can be used to co-design libraries by suggesting favorable compositions as well as favorable layout styles. Finally, VCVs can be turned into test-chips that are guaranteed to cover all identified patterns with the aid of self-testing features. An extremely regular library was developed in 16-nm FinFET technology and is used to showcase our pattern analysis in which DFM quality is shown to be improved with respect to commercial libraries. Our silicon results demonstrate the feasibility of turning the VCV approach into real silicon test chips.

Routing closure and design-for-manufacturability (DFM) challenges exacerbate nonrecurring engineering (NRE) costs, a steep barrier to entry for advanced sub-20-nm CMOS nodes, making low-volume fabrication of integrated circuits (ICs) almost intangible. For ICs in which the cost of design dominates the fabrication, we seek to trade some amount of chip area to lower NRE costs. To this end, we consider designing logic cell layouts for easier routing and DFM closure. We accustom a layout simplification and reuse approach to build standard cell libraries such that good pin access and layout regularity are ensured for all cells. Using a commercial 14-/16-nm technology, we developed two 100-cell logic cell libraries that are, respectively, 9 and 10.5 metal tracks tall. Our routing experiments on multiple designs show that taller cells can endure 20% higher placement density while reducing the number of design rule check (DRC) violations by four orders of magnitude compared with a commercial 7.5 track library. Silicon measurements show that taller cells can enable faster design closure in ICs with stringent performance requirements at the cost of a marginal power overhead. Finally, our logic cell design approach can make advanced CMOS nodes more affordable for low-volume design.

In this paper, a straightforward and effective method to identify threshold logic function (TLF) is presented. Threshold logic is a promising alternative to conventional Boolean logic due to its suitability for emerging technologies, like memristors, quantum-dot cellular automata, resonant tunneling device, and spintronic devices. Identification and synthesis of TLF are essential tasks in a design flow based on such a logic strategy. The proposed method relies on irredundant sum-of-products Boolean function description form and exploits both ordering of variables and system of inequalities to assign the variable weights and the function threshold value. This is the first heuristic algorithm able to identify all threshold functions with up to six variables, being also more effective than other heuristic methods for functions with a larger number of variables. For functions obtained from k -cuts of benchmark circuits, experimental results demonstrated effectiveness near to 100% when compared to exact methods, even when the number of function variables increases. The execution time of the proposed approach is similar to related heuristic methods, being faster than integer linear programming-based algorithms.

Transistor scaling is the major contributor toward continuous improvement of circuit performance. However, the reduction of transistor dimensions increases several fabrication and design challenges. In this sense, several post CMOS devices are being investigated. Recently, the magnetoresistive spin-diode was proposed and the possibility to implement logic gates exploiting this kind of device has been demonstrated. The spin-diode technology has the INV, NOR2 and XNOR2 as basis logic functions, which is quite different from the CMOS basic gates. This paper proposes an algorithm that improves the state-of-the-art synthesis algorithm for the spin-diode technology. Also, this paper presents some optimized designs of functions that appear frequently in circuits. Results show a reduction of more than 3% in number of diodes, compared to the state-of-the-art algorithm.

This paper presents a new approach for Boolean decomposition based on the Boolean difference and cofactor analysis. Two simple tests provide sufficient and necessary conditions to identify AND and exclusive-OR (XOR) decompositions. The proposed method can decompose an n-input function in O(n • log n) cofactor and O(n) equivalence test operations. Recently, 2-to-1 multiplexers (MUX) have also been used to perform such decomposition. However, MUX with more inputs has been neglected. We provide sufficient and necessary conditions to obtain MUX decompositions of functions with an arbitrary number of inputs.

This paper presents two contributions to logic synthesis for memristive stateful logic. Firstly, we demonstrate the necessity to correct results provided by existing logic synthesis methods to ensure the expected computation. Secondly, we propose the concept of multi-memristor implication as a generalization of multi-input implication. Experimental results have shown a reduction of 6.5% in the number of operations when compared to previous works.

This paper presents the 15nm FinFET-based Open Cell Library (OCL) and describes the challenges in the methodology while designing a standard cell library for such advanced technology node. The 15nm OCL is based on a generic predictive state-of-the-art technology node. The proposed cell library is intended to provide access to advanced technology node for universities and other research institutions, in order to design digital integrated circuits and also to develop cell-based design flows, EDA tools and associated algorithms. Developing a 15nm standard cell library brings out design challenges which are not present in previous technology nodes. Some of these challenges include double-patterning for both metal and poly layers, a very restrictive set of physical design rules, and the demand for lithography-friendly patterns. This paper discusses the development of the library considering the challenges associated with advanced technology nodes.

In this paper, a novel method to synthesize circuits based on threshold logic gates (TLG) is proposed. Synthesis considering TLGs is quite relevant, since threshold logic has been revisited as a promising alternative to conventional CMOS integrated circuits due to its suitability to emerging technologies, such as tunneling diodes, memristors and spintronics devices. A constructive process is applied to generate optimized TLG networks taking into account multiple goals and design costs, including gate count, logic depth and number of interconnections. Experiments carried out over MCNC benchmark circuits have shown an average gate count reduction of circa 32%, reaching up to 54% in some cases, in comparison to related approaches.

Every Boolean function has a unique property called Minimum Decision Chain (MDC). This paper proposes an effective way to compute this property for arbitrary functions. The proposed method is very efficient when compared to a more direct and intuitive approach, that is used as the reference for performance analysis. Different examples have been evaluated, and the results are discussed. The proposed method is able to compute the MDC value in order of milliseconds, allowing the use of MDC computation to guide logic synthesis algorithms.

This paper introduces a new algorithm for Boolean factoring. The proposed approach is based on a novel synthesis paradigm, functional composition, which performs synthesis by associating simpler sub-solutions with minimum costs. The method constructively controls characteristics of final and intermediate functions, allowing the adoption of secondary criteria other than the number of literals for optimization. This multi-objective factoring algorithm presents interesting features and advantages when compared to previous works.