Stochastic computing offers low-power and compact arithmetic for neural network inference, but achieving fault tolerance typically requires long bitstreams that create latency bottlenecks for real-time applications. This work introduces an adaptive-precision framework for fault-tolerant stochastic long short-term memory (SLSTM) networks that dynamically assigns stochastic number lengths based on computational criticality. The proposed Cell-based Gradient Sensitivity Search (CGSS) algorithm identifies the most faultsensitive LSTM cells through gradient-based analysis, enabling targeted allocation of longer bitstreams to critical computations while using shorter, low-latency bitstreams for less sensitive operations. The proposed adaptive-precision SLSTM accelerator validates our approach by achieving up to $3.4 \times$ latency reduction, 40% area savings, and 58% power reduction while maintaining fault tolerance equivalent to fixed highprecision SLSTM designs under higher fault rates. These results demonstrate that criticality-guided adaptive-precision is important for making fault-tolerant stochastic neural networks practically viable in resource-constrained environments.

The continuous wavelet transform (CWT) is essential for analyzing non-stationary signals in edge computing, but traditional implementations are limited by high power demands, particularly in resource-constrained environments. Stochastic computing (SC), which leverages probabilistic bit-streams and compact arithmetic units, provides a promising alternative for ultra-low-power CWT designs. However, such circuits are vulnerable to transient faults and involve careful power-reliability trade-offs. This work presents the first SC-based CWT hardware design aimed at applications with severe resource constraints, including power consumption, accuracy, and fault tolerance. We comprehensively analyzed our design, which features a Sobol-based pseudo-random number source and accumulative parallel counter-based addition. In a fault-free environment, this design achieves an 84% power reduction over non-SC CWTs and a 37% reduction over other SC designs. It also achieves up to 64% area savings and reduces latency by 8×. Under a 30% fault rate, our design improves RMSE by 74% over binary CWTs and 32% over other SC implementations.

Human activity recognition (HAR) is a challenging area of research with widespread applications in human-computer interaction. Recent advances in neural networks (NNs) have greatly improved the methods of HAR feature extraction from wearable sensor data and increased the interest in their classification using NNs. While most prior work has relied on software implementations of NN-based HAR, we investigate for the first time hardware implementations for use in resource-constrained edge devices. Emerging edge and near-sensor systems must avoid costly communication with the cloud and perform complex classification tasks locally. This points to using low-area hardware technology such as stochastic computing (SC) and enhanced feature extraction methods such as wavelet transform (WT). We explore the wavelet-assisted stochastic-enabled neural network (WASENN) design for HAR. The NN types we consider are convolutional neural networks and long short-term memory networks. We study both partial and full versions of WASENN and evaluate their performance and resource utilization on the UCI HAR and WISDM datasets. Our hardware synthesis results show the superiority of the wavelet transform in accuracy and size. They also show that SC reduces area and power by 32% and 74% respectively with little impact on classification accuracy.

Stochastic computing (SC) provides low-area, power-efficient hardware solutions suitable for edge systems, but its scalability poses challenges due to its precision limitations, especially in noisy environments. This paper investigates the fault tolerance of key SC components, such as stochastic number generators (SNGs) and activation functions (AFs), within recurrent and sequential networks like long short-term memory (LSTM) networks. We inject bit-flip faults into a network’s most sensitive inputs, weights and AFs, and study fault propagation across different network layers. Our findings reveal that SC component choices significantly influence fault tolerance. For example, networks using Sobol-based SNGs with tanh AFs exhibited stronger resilience than those with LFSR-based SNGs and ReLU AFs, by maintaining higher accuracy under fault conditions. However, the accuracy of the networks declined significantly under simultaneous faults in inputs, weights and AFs. Additionally, while increasing stochastic number lengths improved fault tolerance, they also increased latency. Nevertheless, the SC networks achieved up to 54% area and 72% power savings, making them ideal for resource-constrained applications. We also found that there is a trade-off between efficiency and fault tolerance: SC designs that focus on resource efficiency may struggle in noisy environments, where fault-tolerant SC designs are more effective. This implies that fault resilience in SC architectures depend heavily on design choices and cannot be assumed inherent across all configurations.

Recent advances in near-sensor computing have prompted the need to design low-cost digital filters for edge devices. Stochastic computing (SC), leveraging its probabilistic bit-streams, has emerged as a compelling alternative to traditional deterministic computing for filter design. This paper examines error tolerance, area and power efficiency, and accuracy loss in SC-based digital filters. Specifically, we investigate the impact of various stochastic number generators and increased filter complexity on both FIR and IIR filters. Our results indicate that in an error-free environment, SC exhibits a 49% area advantage and a 64% power efficiency improvement, albeit with a slight loss of accuracy, compared to traditional binary implementations. Furthermore, when the input bit-streams are subject to a 2% bit-flip error rate, SC FIR and SC IIR filters have a much smaller performance degradation (1.3X and 1.9X, respectively) than comparable binary filters. In summary, this work provides useful insights into the advantages of stochastic computing in digital filter design, showcasing its robust error resilience, significant area and power efficiency gains, and trade-offs in accuracy compared to traditional binary approaches.

For emerging edge and near-sensor systems to perform hard classification tasks locally, they must avoid costly communication with the cloud. This requires the use of compact classifiers such as recurrent neural networks of the long short term memory (LSTM) type, as well as a low-area hardware technology such as stochastic computing (SC). We study the benefits and costs of applying SC to LSTM design. We consider a design space spanned by fully binary (non-stochastic), fully stochastic, and several hybrid (mixed) LSTM architectures, and design and simulate examples of each. Using standard classification benchmarks, we show that area and power can be reduced up to 47% and 86% respectively with little or no impact on classification accuracy. We demonstrate that fully stochastic LSTMs can deliver acceptable accuracy despite accumulated errors. Our results also suggest that ReLU is preferable to tanh as an activation function in stochastic LSTMs

Human activity recognition (HAR) is a challenging area of research with many applications in human-computer interaction. With advances in artificial neural networks (ANNs), methods of HAR feature extraction from wearable sensor data have greatly improved and have increased interest in their classification using ANNs. Most prior work has only investigated the software implementations of ANN-based HAR. Here, we investigate, for the first time, two novel hardware implementations for use in resource-constrained edge devices. Through architecture exploration, we identify first a hybrid ANN we call DCLSTM incorporating the convolutional and long-short-term memory techniques. The second is a much more compact implementation WCLSTM that uses wavelet transforms (WTs) to enhance feature extraction; it can achieve even better accuracy while being smaller and simpler; it is therefore the better choice for resource-constrained applications. We present hardware implementations of these ANNs and evaluate their performance and resource utilization on the UCI HAR and WISDM datasets. Synthesis results on an FPGA platform show the superiority of the WT-assisted version in accuracy and size. Moreover, our networks achieve a better accuracy than earlier published works.