VLDB 2026 Research / reviewers in the wild / expert
Piratach Yoovidhya
dblp:321/3832
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2022
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 87% Hardware accelerators and domain-specific architectures · 13% |
Topics — the 2 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › memory hierarchy
cache hierarchy |
0.6 | 1 | 2022 | täk¯: a polymorphic cache hierarchy for general-purpose optimization of data movement · ISCA 2022 |
Memory systems › memory access optimization
data movement reduction |
0.6 | 1 | 2022 | täk¯: a polymorphic cache hierarchy for general-purpose optimization of data movement · ISCA 2022 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | täk¯: a polymorphic cache hierarchy for general-purpose optimization of data movementabstractCurrent systems hide data movement from software behind the load-store interface. Software's inability to observe and respond to data movement is the root cause of many inefficiencies, including the growing fraction of execution time and energy devoted to data movement itself. Recent specialized memory-hierarchy designs prove that large data-movement savings are possible. However, these designs require custom hardware, raising a large barrier to their practical adoption. Brian C. Schwedock, Piratach Yoovidhya, Jennifer Seibert, Nathan Beckmann |
ISCA | 2 |