Pain-level detection is vital to determine proper medical treatment. Existing self-reporting, behavioral, and image-based pain detection methods typically lead to high costs for professional staff and clinical equipment and also have a high risk of leaking sensitive information, which could be exploited by adversaries to learn gender, age group, and underlying health conditions. To address these challenges, we propose a privacy-aware voice-based pain-level detection framework, which extracts frequency-domain characteristics from audio files, removes the gender-sensitive features from the identified characteristics, and trains a convolutional neural network (CNN) to perform 3-level pain classification. Our preliminary analysis and experiments based on a commonly adopted database (TAME Pain dataset) indicate that log-Mel spectrogram and zero-crossing rate are two promising voice features for effective pain-level classification. We further extend our study to a nonverbal dataset, VIVAE (Variably Intense Vocalizations of Affect and Emotion Corpus), and confirm that the identified voice features are applicable to both verbal and nonverbal patients for pain classification.

In-Sensor Computing (ISC) systems emerge as a promising alternative to save energy on massive data transmission, analog-to-digital conversion, and ineffective processing. While the new paradigm shift of ISC systems gains increasing attention, the highly compacted systems could incur new challenges from a hardware security perspective. This work conducts a literature review to highlight the research trend of this topic and then performs comprehensive analyses on the root of security challenges. To the best of our knowledge, this is the first work that compares the security challenges of traditional sensor-involved computing systems and emerging ISC systems. We conduct a comprehensive analysis of ISC's design phases to identify significant vulnerabilities and attack surfaces. Furthermore, new attack scenarios are predicted for board-, chip-, and device-level ISC systems. Three proof-of-concept demos are provided to reveal the consequences of the attacks for three different levels. Our findings emphasize the urgent necessity for sophisticated defense mechanisms and inspire researchers to work on new countermeasure designs against unique hardware security threats in ISC systems.

In-sensor computing (ISC) represents a paradigm shift in sensor integration technologies. ISC system combines sensing and processing elements on a single chip, enabling real-time processing and reducing computation latency by eliminating massive data transfer and analog-to-digital conversion. However, due to the high integration of sensors and computation units, ISC could suffer from new security attacks that have not been explored yet. In this work, we investigate a covert channel attack that leverages the analog nature of ISC to showcase the feasibility of security attacks and severe consequences in the context of real applications. We envision that this research paper will inspire more researchers to brainstorm new defense mechanisms for the emerging ISC.

In-Sensor Computing (ISC) systems integrate sensing and computing units within a single device, enabling low-latency, energy-efficient applications through direct analog-to-feature conversion. However, the intrinsic tight coupling between sensing and computational components introduces significant security vulnerabilities. These arise particularly in scenarios where adversaries have a good understanding of the analog computation mechanisms and could tamper with the ISC device, potentially allowing for manipulation, inference, or extraction of sensitive data. This work introduces exploitable backdoors in ISC that encode the output of the analog computation unit to create covert channels. Through theoretical modeling and empirical case studies, we investigate two ISC-specific covert channels: a logic covert channel and a frequency covert channel. These channels are established by deliberately manipulating the analog computation unit co-integrated with sensing materials on a shared substrate, thereby enabling adversaries to exfiltrate sensitive information, posing substantial threats to the security and privacy of real-world ISC applications.

Multi-tenant Field Programmable Gate Arrays (FP-GAs) have been widely integrated into cloud and edge computing environments to save hardware costs. Unfortunately, shared FPGAs among multiple users make the system vulnerable to new security threats. For instance, a voltage-drop attack exploits transient voltage fluctuations on the FPGA power distribution network to cause critical faults. Existing works either check combinatorial loops or utilize numerous on-chip sensors to detect fault attacks. Recent literature shows that some advanced power waster units can bypass combinatorial loop checks and defeat attack localization. To counteract the powerful fault attacks, this work proposes an on-chip sensor placement strategy to detect and localize the source of voltage-drop attacks. An attack mitigation framework integrates the proposed sensor placement strategy and a new assessment metric to improve the sensitivity of attack localization. Our case study shows that the proposed method achieves a 100% success rate in attack localization. Furthermore, experimental results show that the proposed method reduces the localization time by 90% and the number of deployed sensors by 89% over existing works.

Multi-tenant Field-programmable Gate Arrays (FPGAs) in cloud service are vulnerable to remotely exploitable attacks, among which power waster circuit (PWC)-based fault attacks have been demonstrated as a highly feasible one. PWC generates high switching activities and causes a sudden voltage drop in the power distribution network (PDN), resulting in a delay of signal propagation and FPGA malfunction. Existing countermeasures deploy bitstream checking methodologies or deploy numerous on-chip sensors to mitigate voltage-drop attacks. Since new PWCs without combinatorial loops and a multi-source attack are emerging, the current countermeasures lack the ability to mitigate new security challenges in multi-tenant FPGAs. To address these issues, a Signal-slowdown (SS)-based fault attack mitigation (S 2 FAM) method is proposed to detect both combinatorial (ring-oscillator (RO)-based PWC) and non-combinatorial (ring-oscillator Flip-flop (ROFF)-based PWC) loop-based attacks and precisely pinpoint the attack locations. A new calibration technique in S 2 FAM facilitates to identify and remove unstable sensor data, thus significantly reducing false positives. Moreover, the proposed method localizes both the single- and multi-source attacks in the FPGA by utilizing a tenant-level SS ranking (TSSR)-based algorithm. Experimental results show that the proposed method reduces the false alarm by 45.8%, compared to the existing works. Our proposed algorithm for attack localization achieves a 100% success rate and reduces the attack localization area for a multi-source attack by 25.2% than an existing countermeasure. The successful localization is achieved by utilizing our proposed method within 2 \(\mu\) s (200 clock cycles) of attack duration. The proposed signal slowdown metric with the calibration process reduces the number of on-chip sensors by 78% and the localization time by 90.5%, compared to the baseline.

Real-time health monitoring systems generate a large volume of sensing data, requiring tremendous processing time and storage space. Orthogonal to existing approximate computing mechanisms, this work proposes a Feature-Driven Approximation (FDApx) method to address the pressing need for fast data processing and a limited storage budget in wearable health monitoring devices. The proposed FDApx method reverses the features interested in high-level applications to derive approximation thresholds to retain feature-critical information, rather than aimlessly storing and transmitting all raw data. Case studies in an insole sensing system for fall risk assessment show that FDApx can reduce the data size by up to 87% over raw data and up to 85% over 2-bit precision reduction-based approximation. The approximation from FDApx only results in up to a 2% deviation in swing time; in contrast, the approximation based on precision reduction causes a 30% deviation in the same gait feature1.

Safety-critical systems such as automated embedded or industrial systems have a strong dependency on the trustworthiness of data collection. As sensors are the critical component for those systems, it is imperative to address the attack resilience of sensors. System-level defense methods typically do not differentiate the root cause and recover the system from attack with the same procedure, thus resulting in unnecessary costs. In this work, we propose a circuit-level solution to handle security challenges in a temperature sensor. The complementary current-temperature characteristics are exploited to generate a constant current reference for attack detection. Experimental results show that our sensor is capable of detecting an under-powering attack from a significant signal vibration in the constant current reference. Furthermore, our sensor can detect an active analog Trojan by analyzing substantial current deviation in a wide range of temperatures. These high sensitivities against the under-powering and analog Trojan attacks make the sensor resilient against attacks at the circuit level. The proposed sensor consumes 17% less power and achieves 11% higher power-supply-rejection-ratio than existing work.

More and more digitized techniques and network connectivity are deployed to advanced manufacturing to enable remote system monitoring and automated production; however, this trend also leads to the traditional assumption of security in manufacturing not holding true any longer. For instance, the option of remote access makes advanced manufacturing infrastructures vulnerable to various security attacks from physical devices to cyberspace. Existing literature that addresses the attacks in advanced manufacturing is mainly at the network level. In this work, we study the role of hardware security in the process of advanced manufacturing. More specifically, our analysis focuses on the security vulnerability of sensors, local data processing nodes, and the interface implementation for standardized communication protocols. Unique attack examples such as hardware Trojan, interface sniffing, and fraudulent data injection attacks are provided in this work to highlight the unique challenges of attack detection and mitigation in advanced manufacturing.