Despite decades of mitigation efforts, memory corruption bugs remain a dominant source of security vulnerabilities. CHERI, a capability-based architecture, directly targets this problem by replacing traditional pointers with Capabilities that encode bounds, permissions, and tamper-protection tags. However, CHERI represents a significant architectural intervention that impacts not only the processors core, but the entire Hardware/Software platform. System-level evaluation methods, such as Virtual Prototypes (VPs), have shown to be highly valuable for exploring, validating, and optimizing such complex Hardware/Software systems. This paper introduces the first open-source SystemC/TLMbased CHERI-enhanced RISC-V VP. The VP comes with support for Virtual Memory Management (VMM) and is capable of executing complex software stacks, such as the general purpose and memory-safe CheriBSD operating system. A verification using TestRIG demonstrates the VP’s robustness, passing 2.15 million test cases. A case study with CheriBSD and 10 representative, demanding benchmark workloads highlights the VP’s capability to simulate complex CHERI-enabled systems and to provide valuable insights for Hardware/Software co-design. The CHERI-enhanced VP, along with the Software used in our case study is available as open-source on GitHub.

In this paper, we enhance RVVTS, an open-source framework for testing RISC-V vector instructions, to enable comprehensive floating-point (FP) verification across various RISC-V simulators and FP libraries. Our enhanced RVVTS, referred to as FP-RVVTS, adds support for the RISC-V FP extensions (F, D, Zfh) through a novel context-free grammar specification with annotations, strengthened automatic single-instruction isolation, and improved failure cause analysis.In the experiments we show that FP-RVVTS generates FP test sets achieving over 95% functional coverage, reveals critical bugs in several RISC-V simulators, and, using isolated instructions, supports to narrow down the causes of failures.

We present a highly automated, open-source RTL verification framework for the RISC-V Vector Extension (RVV) 1.0 that extends the open-source RVVTS framework by adding RTL support and a novel Automated Failure Categorization (AFC) stage for scalable result analysis. Using the most recent RTL of the silicon-proven Ara vector processor as DUT, we generate RVV test sets that encompass both positive and negative testing, and achieve over 96% functional coverage – significantly exceeding our evaluated baseline, which achieves only 11.04%. Our framework detects more than 82k deviations, automatically minimizes about 97% of them, and clusters observed failures into 16 distinct categories.

TheInstruction Set Simulators (ISSs) used in Virtual Prototypes (VPs) are typically implemented as interpreters with the goal to be easy to understand, and fast to adapt and extend. However, the performance of instruction interpretation is very limited and the ever-increasing complexity of Hardware (HW) poses an increasing challenge to this approach. In this paper, we present optimization techniques for interpreter-based ISSs that significantly boost performance while preserving comprehensibility and adaptability. We consider the Risc-V Iss of an existing, SystemC-based open-source VP with extensive capabilities such as running Linux and interactive graphical applications. The optimization techniques feature a Dynamic Basic Block Cache (DBBCache) to accelerate ISS in-struction processing and a Load/Store Cache (LSCache) to speed up ISS load and store operations to and from memory. In our evaluation, we consider 12 Linux-based benchmark workloads and compare our optimizations to the original VP as well as to the very efficient official RISC-V reference simulator Spike maintained by RISC-V International. Overall, we achieve up to 406.97 Million Instructions per Second (MIPS) and a significant average performance increase, by a factor of 8.98 over the original VP and 1.65 over the Spike simulator. To showcase the retention of both comprehensibility and adaptability, we implement support for RISC-V half-precision floating-point extension (Zfh) in both the original and the optimized VP. A comparison of these implementations reveals no significant differences, ensuring that the stated qualities remain unaffected. The optimized VP including Zfh is available as open-source on GitHub.

Transaction-level debugging in Virtual Prototypes (VPs) remains challenging due to the sheer number and intricate nature of interactions between software and hardware components. This paper presents ProtoLens, the first open-source tool for dynamic visualization of Transaction Level Modeling (TLM) transactions in SystemC-based VPs. Integrated with the open-source RISC-V VP++, ProtoLens provides an interactive web front-end that displays architecture-aware transaction flows in real-time. It captures transaction data via a lightweight extension of the TLM bus and enriches it with peripheral-specific views through user-defined modules, so-called Transaction View Modules (TVMs). Additionally, ProtoLens supports integration with software debuggers, allowing synchronized transaction inspection and control of the simulation flow. This enables developers to efficiently analyze issues such as incorrect memory mappings, unexpected peripheral behavior, and to better understand the overall system architecture.Two case studies highlight the capabilities of ProtoLens: one demonstrates how it complements classical debugging in a bare-metal software example, and the other showcases its ability to reconstruct real-time graphics output from a Linux-based game.

In this paper we introduce the first free- and open-source SystemC TLM based RISC-V Virtual Prototype (VP) with support for the RISC-V “V” Vector Extension (RVV) Version 1.0. After an introduction to RVV, we present the integration of RVV and its 600+ instructions into an existing VP leveraging code generation for over 20k Lines of Code (LoC). Moreover, we describe the verification of the resulting VP using the Instruction Sequence Generator (ISG) FORCE-RISCV and the Instruction Set Simulator (ISS) riscvOVPsim. Our case studies demonstrate the benefits of the RVV enhanced VP for system-level evaluation. We present non-vectorized and vectorized variants of two common algorithms which are executed on the VP with varying parameters. We show that by comparing the number of simulated execution cycles, we can derive valuable assessments for the design of RVV micro-architectures.

Testing complex RISC-V extensions such as RISC-V Vector (RVV) with its 600+ highly configurable instructions is crucial. For this reason, test suites have been developed over the last years, including both hand-written and automatically generated tests. Although the process of running these tests is often highly automated, a significant portion of the work, namely the result analysis, has to be conducted manually after the run.

Today, Virtual Prototypes (VPs) are heavily used to enable early software development and to accelerate the design process. The aim of this work is twofold: (i) enable the early development of interactive graphical applications running on Linux, and (ii) provide an easy-to-use and configurable solution for RISC-V. In this paper, we present GUI-VP Kit. GUI-VP Kit includes GUI-VP, a greatly extended and improved RISC-V VP, as well as configurations to build a runnable Linux environment, and input/output drivers that form the interface between peripherals and Linux applications. In our experiments employing GUI-VP Kit, we show that well-known X-applications can be executed in GUI-VP using a VNC network connection. Moreover, we demonstrate reasonable speed for a Linux port of a classic first-person 3D-game.

In this paper, we present RVVRadar, a framework to support the programmer over the four major steps of development, verification, measurement, and evaluation during the vectorization process of an algorithm. We demonstrate the advantages of RVVRadar for vectorization on several practical relevant algorithms. This includes in particular the widely-used libpng library where we vectorized all filter computations resulting in speedups of up to 5.43. We made RVVRadar as well as all benchmarks (including the RVV-based libpng) open source.