Power side-channel attacks are among the most effective physical attacks, threatening the security of circuits such as cryptographic circuits by exploiting information leakage from their physical implementation. Among various masking and hiding countermeasures that have been proposed, Ring Oscillator (RO)-based solutions are considered low-overhead circuitry addons that can be integrated into different circuits to hide the data dependency of power consumption by adding noise to their power signatures. The Three-Independent-Gate Reconfigurable Field-Effect Transistor (TIG-RFET) is an emerging technology that offers runtime reconfigurability between N-type and P-type operation, supports both low-VTand high-VTmodes, and provides an internal wired-AND function, making it a strong candidate for efficient implementation of various hardware security methods. In this paper, we propose a novel reconfigurable RFET-based RO that provides controllable frequency through RFET-based inverters with reconfigurable delay. Using these ROs, we introduce a countermeasure called RETRO, which can generate noise by varying both the amplitude and frequency of power consumption. To evaluate the efficacy of RETRO, we applied it to the Piccolo S-box, a lightweight cryptographic circuit, and simulation results demonstrate that it effectively enhances resilience against Correlation Power Analysis (CPA). Furthermore, we show that reconfigurable frequency broadens the noise spectrum, making filtering considerably more difficult.

Logic locking protects hardware intellectual property (IP) against piracy, but recent machine learning (ML)-based attacks have shown highly accurate key prediction against this technique. However, existing attacks have three main shortcomings: (1) they lack a statistical analysis regarding the size of leakage locality and they lack a formal leakage model, leading to a back-and-forth cycle of attacks and defenses; (2) they lack circuit-level analysis for choosing suitable ML models; and (3) they limit attackers to the same toolset available to security designers leaving a gap in understanding tool-agnostic vulnerabilities. In this paper, we analyze gate-based obfuscation and provide statistical evidence that leakage is concentrated within a 2–3 hop key locality. We propose a first-of-its-kind information-theoretic formalization of structural leakage, showing that locking remains vulnerable when it introduces independent, localized effects after re-synthesis, regardless of the locking approach. Building on this, we design compact structural and simulation-based functional features that capture local leakage around key gates. Using these features, we introduce EAGEL, an explainable and generalized security assessment framework that removes the attacker’s dependence on the designer’s synthesis toolchain and empirically validates our leakage formalization. EAGEL achieves up to \(98\%\) key prediction accuracy and \(99.5\%\) prediction certainty, outperforming complex state-of-the-art GNN-based attacks by up to \(11\%\) and on average by \(8.58\%\), with a 3.4 × speedup.

Because of the globalization of IC manufacturing and to protect IP integrity and confidentiality, circuit obfuscation techniques have been developed. These methods secure the circuit through obfuscation approaches. Recently, advanced machine learning (ML)-based structural attacks have been introduced that employ the structure of the circuit to reverse the obfuscation mechanism. These attacks use ML-based approaches to analyze and neutralize obfuscation schemes without requiring unlocked functional circuits, posing a significant challenge to IP security. To counter ML-based attacks, in this article, we first analyze the sources of structural leakages of the interconnect obfuscation technique, one of the most robust IP protection mechanisms. We conduct a first-of-its-kind analysis of the circuit’s netlist graph, obfuscated using interconnect obfuscation, to evaluate its robustness against link prediction techniques. Based on our analysis, we introduce a security assessment tool that evaluates the strength of the obfuscation technique in omitting structural leakages that lead to the success of ML-based attacks. Our assessment tool reveals that previous obfuscation methods fall short of achieving their intended security levels. This leads to our second contribution, which is proposing ML-SafeConnect, an interconnect obfuscation technique that protects the obfuscated substructures by completely eliminating distance-based structural leakages. Using our assessment tool and state-of-the-art ML-based attack, we demonstrate that our obfuscation mechanism surpasses previous interconnect obfuscation techniques in preventing structural leakages. We show that ML-SafeConnect completely thwarts ML-based attacks for all benchmark circuits by decreasing the accuracy of state-of-the-art attacks to below 50%.

As emerging computing paradigms push beyond the limitations of traditional CMOS-based computing using Von Neumann architectures, there is a growing need to rethink and extend Electronic Design Automation (EDA) methodologies to support their unique characteristics. These paradigms—including Approximate Computing, In-Memory Computing, Reconfigurable Field-Effect Transistors (RFETs), and Photonic Computing—represent diverse and promising directions beyond conventional digital design. Collectively, they offer transformative potential for achieving significant improvements in energy efficiency, computational speed, and architectural scalability. For example, application-specific approximate computing enables the design of custom arithmetic circuits that exploit application-level error resilience, allowing for optimized accuracy–power–performance–area (PPA) trade-offs in error-tolerant applications. Similarly, processing-in-non-volatile memories, such as those based on Ferroelectric Field-effect Transistors (FeFETs), enhances energy efficiency by enabling analog computation—particularly for operations like matrix multiplication—directly within the memory arrays. The intrinsic polymorphism of RFETs supports compact, multifunctional logic gates and introduces new opportunities for circuit-level obfuscation and security-aware design. Likewise, photonic analog wavefront computing offers substantial gains in latency and energy efficiency by encoding and processing information in the analog optical domain, leveraging phenomena such as diffraction and interference to perform computation at the speed of light. However, they also introduce a host of new challenges in circuit and architecture design, such as vast and irregular design spaces, analog and non-Boolean behavior, and new device-level constraints that existing EDA tools are not capable of handling. To this end, the current article focuses on the development of efficient and robust EDA frameworks that can enable the practical realization of circuits and architectures in these emerging domains.

While a number of measures have been proposed to protect the integrity of COS hardware, there are some inherent limitations from classical CMOS methods. Those already existing security methods, like logic locking can be improved with emerging technologies such as Reconfigurable Field Effect Transistors (RFETs). RFETs are a special type of doping-free, Schottky transistors which can work as a PFET or NFET as a function of biasing across its gates. In the present study we developed standard cell layouts for dynamic reconfigurable security cells based on three-independent-gated RFETs (TIG-RFETs). They layouts are compatible to an industrial 22nm FDSOI technology, feature the minimum pitch of the baseline technology, and obey all design rules necessary for co-integration. The designs enable a fair area comparison for RFET based digital application for the first time. Based on the sizing constraints from the layouts, a TCAD model of such a TIG-RFET is developed in Sentaurus TCAD to illustrate two biasing schemes for the application of TIGRFETs in this platform: reconfigurability with individual body-bias per transistor and reconfigurability at globally fixed body-bias. Due to the different operation options three variants of reconfigurable 2-XOR-XNOR and 2-NAND-NOR logic cells exhibiting different level of utility are designed. While the smallest dynamic 2-NAND-NOR gate needs roughly double the area of a CMOS 2-NAND gate from the reference library, the smallest 2-XOR-XNOR gate is only 20% larger than a CMOS 2-XOR. To quantify the area overhead for hardware security applications we calculated the number of logic locking gates that can be added per area overhead for a given circuit, here the ISCAS-85 C6288 benchmark circuit, as an example. Dynamic replacement based logic locking with TIG-RFETs shows to allow up to double the number of keys compared to classical CMOS logic locking per area overhead. Therefore, this work allows a realistic view on the application of RFETs in hardware security and its co-integrability along with some design constraints from an industrial PDK.

Power attacks are effective side-channel attacks (SCAs) that exploit weaknesses in the physical implementation of a cryptographic circuit to extract its secret information like encryption key. In recent years, emerging technologies have unlocked new possibilities in designing effective SCA countermeasures with less overhead. Reconfigurable Field-Effect Transistors (RFETs) are a type of beyond-CMOS technology that can be configured at run-time to act as an NFET or PFET transistor and provide two or more independent gates. These features make RFETs potent candidates for implementing hardware security techniques like logic locking and SCA countermeasures. In this paper, we propose REDCAP, a method to add randomness to the power traces of a circuit, employing compact reconfigurable RFET-based gates to make the design resilient against power SCAs. First, we explain the construction and control of reconfigurable blocks with isofunctional configurations inside the circuit. Then, we provide an algorithm to efficiently compose the reconfigurable blocks with other circuit parts to minimize the overhead and enable designers to determine the granularity of the reconfiguration. To evaluate our approach, we performed a Correlation Power Attack (CPA) on the S-box of the Piccolo and PRESENT, two lightweight cryptographic circuits, and the results show that REDCAP can highly enhance the resilience of the circuit against power SCAs.

Machine learning (ML) and algorithmic structural attacks have highlighted the possibility of utilizing structural leakages of an obfuscated circuit to reverse engineer the locking mechanism. These structural leakages are rooted in security-agnostic synthesis tools that lead to discernible patterns within the vicinity of the locking substructures. This paper has two contributions. Firstly, we present the innovative Flip-lock, a novel approach that utilizes flip-flops along logic gates to prevent synthesis tools’ structural leakages. As this is the first work that incorporates flip-flops in locking structures, our second contribution is the development of a comprehensive analysis tool designed to identify and assess potential structural leakages in the vicinity of flip-flops within circuits. We name our tool Flip-attack. We employ the Flip-attack analysis to strengthen Flip-lock’s resilience against potential future attacks. Our findings demonstrate that Flip-lock possesses the capability to neutralize all existing state-of-the-art structural attacks effectively. Furthermore, by enhancing Flip-lock through the incorporation of our analysis tool, we establish a robust defense mechanism that can safeguard the circuit’s security against potential future threats.

The globalization of the IC manufacturing flow has exposed intellectual property (IP) to many untrustworthy entities. As a result, security should be considered a new paradigm in designing circuits to protect the integrity and confidentiality of the IP. Logic locking is a holistic design-for-trust (DFT) technique that can protect circuits against IP piracy and reverse engineering. However, a large body of recent research has demonstrated successful methods of recovering the secret key and restoring the original functionality of existing locking systems. Although SAT attack has been a de facto technique to break the logic locking, the threat model and efficiency of this attack have been questioned recently. To overcome these shortcomings, researchers have proposed powerful structural attacks that break the locked circuits without the need for functionally unlocked circuits (Oracle). Among structural attacks, machine learning (ML)-based attacks are the most potent attacks as they harness the power of neural networks to learn traces of the locking structures and use this knowledge to reverse back and neutralize the locking scheme. Among ML approaches, GNN (graph neural networks)-based attacks are shown to be the most capable tools that attackers can employ as they exploit graph structures inherent to a circuit’s netlist. In this paper,(1)We discuss the inherent structural weaknesses of the logic locking techniques.(2)Knowing these weaknesses, we investigate the challenges of protecting circuits against GNN-based attacks.(3)We propose GNN-resilient Interconnect-based obfuscation (GRIN) and GNN-resilient Gate-based Obfuscation (GREGO) logic locking schemes with learning resilient structures. We evaluate our secure schemes using ISCAS-85 and ITC-99 benchmarks and provide comprehensive security and overhead analysis of our proposed schemes.

Side-Channel Attacks (SCAs), which are always considered a severe threat to the security of the cryptographic circuits, today can also be employed to extract IP secrets and neural network models. Hence, developing novel security solutions at different design levels is crucial. In this paper, we explore recent countermeasures at the circuit, algorithmic, and microarchitecture levels. First, we explain how Reconfigurable Field-Effect Transistor (RFET), as a beyond CMOS technology, enables us to provide both IP and data protection against SCAs at the circuit level. Second, we investigate an automated method for generating masked circuits as an algorithmic solution, and then we review machine learning-based SCA detection mechanisms at the microarchitecture level. Finally, we discuss emerging threats of SCAs from the industrial point of view.

Machine learning (ML)-based attacks have revealed the possibility of utilizing neural networks to break locked circuits without needing functional chips (Oracle). Among ML approaches, GNN (graph neural networks)-based attacks are the most potent tools that attackers can employ as they exploit graph structures inherent to a circuit’s netlist. Although promising, in this paper, we reveal that GNNs have some impediments in attacking locked circuits. We investigate the limits of the state-of-the-art GNN-based attacks against logic locking and show that we can drastically decrease the accuracy of these attacks by utilizing these limitations in the locking process.

Reconfigurable transistors are a new emerging type of device, which offer the promise to improve the resistance of electronic components against know-how theft. In order to enable a product development of such an emerging device, a cross-layer design enablement strategy is needed, as emerging technologies are not necessarily compatible withstandard tools used in the industry. In ‘CirroStrato’, we aim on the development of such a complete flow enabling CMOS co-integration of reconfigurable transistors, ranging from process adjustments, device modeling, library characterization, physical and logical synthesis up towards sophisticated hardware security tests. In this multi-partner-project (MPP) paper, our aim is to elucidate the overall design enablement flow, as well as current research challenges on the individual stages.

Among the SAT-resilient logic locking techniques, the Stripped-Functionality-Logic-Locking (SFLL) is the most promising solution which can guard the intellectual property against approximate, sensitization, SAT, and structural attacks which target Point-function techniques. However, even the SFLL technique has been shown to be vulnerable to a recent class of structural attacks that identify the perturbation logic. In this paper, we first categorize all possible classes of attacks on SFLL. Then we propose ENTANGLE a novel logic locking technique built upon SFLL that can resist all of these attacks, including the emerging ML-Based attacks. We test our technique against publicly available SFLL attacks. The implementation results show that ENTANGLE can secure large-sized industrial circuits with an average overhead of 11.6 percent and 9.1 percent for area and power, respectively.

Hardware security has been an ever-growing concern of the integrated circuit (IC) designers. Through different stages in the IC design and life cycle, an adversary can extract sensitive design information and private data stored in the circuit using logical, physical, and structural weaknesses. Besides, in recent times, ML-based attacks have become the new de facto standard in hardware security community. Contemporary defense strategies are often facing unforeseen challenges to cope up with these attack schemes. Additionally, the high overhead of the CMOS-based secure addon circuitry and intrinsic limitations of these devices indicate the need for new nano-electronics. Emerging reconfigurable devices like Reconfigurable Field Effect transistors (RFETs) provide unique features to fortify the design against various threats at different stages in the IC design and life cycle. In this manuscript, we investigate the applications of the RFETs for securing the design against traditional and machine learning (ML)-based intellectual property (IP) piracy techniques and side-channel attacks (SCAs).