Xinhao Kong

dblp:323/8118 · DBLP profile ↗
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8ranked-venue papers
3as first author
8since 2021 · last 2026
0009-0005-2628-7112ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 5 · 2 first-author · 5 since 2021Software engineering, systems software and programming languages · 2 · 1 first-author · 2 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021Systems, architecture and hardware · 1 · 1 since 2021
YearPublicationVenuePosition
2026 Phantora: Maximizing Code Reuse in Simulation-based Machine Learning System Performance Estimation
Jianxing Qin, Jingrong Chen 0002, Xinhao Kong, Tianjun Yuan, Zhaodong Wang, Ying Zhang 0022, Tingjun Chen, Alvin R. Lebeck, Danyang Zhuo
NSDI3
2025 OminiAdapt: Learning Cross-Task Invariance for Robust and Environment-Aware Robotic Manipulation
Yongxu Wang, Weiyun Yi, Xinhao Kong
PRICAI3
2024 HAL: Hardware-assisted Load Balancing for Energy-efficient SNIC-Host Cooperative Computing
abstract
A typical SmartNIC (SNIC) integrates a processor comprising Arm CPU and accelerators with a conventional NIC. The processor is designed to energy-efficiently execute network functions frequently used by datacenter applications. With such a processor, the SNIC has promised to notably improve the system-wide energy efficiency of datacenter servers. Nevertheless, the latest trend of integrating accelerators into server CPUs for these functions sparks a question on the SNIC processor’s superiority over a host processor (i.e., server CPU with accelerators) in system-wide energy efficiency, especially under given tail latency constraints. Answering this question, we first take an Intel Xeon processor, integrated with various accelerators (e.g., QuickAssist Technology), as a host processor, and then compare it to an NVIDIA BlueField-2 SNIC processor. This uncovers that (1) the host accelerator, coupled with a more powerful memory subsystem, can outperform the SNIC accelerator, and (2) the SNIC processor can improve system-wide energy efficiency only at low packet rates for most functions under tail latency constraints. To provide high system-wide energy efficiency without compromising tail latency at any packet rates, we propose HAL, consisting of a hardware-based load balancer and an intelligent load balancing policy implemented inside the SNIC. When HAL determines that the SNIC processor cannot efficiently process a given function beyond a specific packet rate, it limits the rate of packets to the SNIC processor and lets the host processor handle the excess. We implement a HAL-enabled SNIC with a commodity FPGA and a BlueField-2 SNIC, plug it into a commodity server, and run 10 popular network functions. Our evaluation shows that HAL can improve the system-wide energy efficiency and throughput of the server running these functions by 31% and 10%, respectively, without notably increasing the tail latency.
Jinghan Huang 0001, Jiaqi Lou, Srikar Vanavasam, Xinhao Kong, Houxiang Ji, Ipoom Jeong, Danyang Zhuo, Nam Sung Kim
ISCA4
2024 Harmonic: Hardware-assisted RDMA Performance Isolation for Public Clouds
Jiaqi Lou, Xinhao Kong, Jinghan Huang 0001, Wei Bai 0001, Nam Sung Kim, Danyang Zhuo
NSDI2
2023 Towards a Manageable Intra-Host Network
abstract
Intra-host networks, including heterogeneous devices and interconnect fabrics, have become increasingly complex and crucial. However, intra-host networks today do not provide sufficient manageability. This prevents data center operators from running a reliable and efficient end-to-end network, especially for multi-tenant clouds. In this paper, we analyze the main manageability deficiencies of intra-host networks and argue that a systematic solution should be implemented to bridge this function gap. We propose two key building blocks for a manageable intra-host network: a fine-grained monitoring system and a holistic resource manager. We discuss the research questions associated with realizing these two building blocks.
Xinhao Kong, Jiaqi Lou, Wei Bai 0001, Nam Sung Kim, Danyang Zhuo
HotOS1
2023 Remote Procedure Call as a Managed System Service
Jingrong Chen 0002, Shihan Lin, Yechen Xu, Xinhao Kong, Thomas E. Anderson, Matthew Lentz, Xiaowei Yang 0001, Danyang Zhuo
NSDI5
2023 Understanding RDMA Microarchitecture Resources for Performance Isolation
Xinhao Kong, Jingrong Chen 0002, Wei Bai 0001, Yechen Xu, Mahmoud Elhaddad, Shachar Raindel, Jitendra Padhye, Alvin R. Lebeck, Danyang Zhuo
NSDI1
2022 Collie: Finding Performance Anomalies in RDMA Subsystems
Xinhao Kong, Yibo Zhu 0001, Huaping Zhou, Zhuo Jiang, Jianxi Ye, Chuanxiong Guo, Danyang Zhuo
NSDI1