Demo Data from VLDB 2026 / reviewers in the wild / expert
Guey-Liou Lan
dblp:324/7646
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1991
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 100% | |
| Computer networks
1 paper |
Physical-layer communications · 100% |
Topics — the 2 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
analog and mixed-signal circuits |
0.0 | 1 | 1991 | Multifunction W-band MMIC receiver technology · Proc. IEEE 1991 |
Integrated circuit design › radio-frequency circuit design
monolithic microwave integrated circuit |
0.0 | 1 | 1991 | Multifunction W-band MMIC receiver technology · Proc. IEEE 1991 |
Methods — techniques the papers use, named apart from their topics
multiplexer design · 0.0gunn oscillator design · 0.0GaAs MMIC process · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1991 | Multifunction W-band MMIC receiver technologyabstractThe development of a W-band (75-110 GHz) monolithic receiver, culminating in a three-chip multifunctional monolithic microwave integrated circuit (MMIC) receiver front-end, is described. The heart of the receiver is a four-channel multiplexer, with each channel possessing its own single balanced mixer and low-noise IF amplifier, all integrated onto a single GaAs chip. Two dual-channel monolithic Gunn oscillators with the drive level and spectral parity to meet system requirements have been developed. The key to the development of the monolithic front-end has been to ensure process compatibility between individual components and the careful partitioning of the chip architecture.> Martin I. Herman, Guey-Liou Lan, James C. Chen, Cheng-Keng Pao |
Proc. IEEE | 2 |