VLDB 2026 Research / reviewers in the wild / expert
Brandon Zink
dblp:325/4463 · also Brandon R. Zink
· DBLP profile ↗
2ranked-venue papers
0as first author
2since 2021 · last 2024
0000-0001-5877-6539ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 2 · 2 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | On Gate Flip Errors in Computing-In-MemoryabstractComputing-in-memory (CIM) architectures that perform logic gate operations directly within memory arrays, in-situ, are particularly effective in addressing memory-induced performance bottlenecks. When paired with nonvolatile memory, energy efficiency in performing bulk bitwise logic operations can reach unprecedented levels. However, unlocking this potential is not possible if functional correctness is compromised. In this paper we present a CIM-specific class of functional errors termed gate flips, where parametric variations make a logic gate behave as another. Through detailed functional and electrical characterization we demonstrate that gate flips stem from a significant subclass of write errors. Accordingly, we introduce an abstract model to enable efficient functional reliability assessment and to guide design decisions in forming universal CIM gate libraries. We also evaluate the impact on the end accuracy of computation using representative benchmarks. Zamshed I. Chowdhury, M. Hüsrev Cilasun, Salonik Resch, Masoud Zabihi, Yang Lv 0003, Brandon Zink, Jianping Wang 0006, Sachin S. Sapatnekar, Ulya R. Karpuzcu |
DATE | 6 |
| 2024 | On Error Correction for Nonvolatile Processing-In-MemoryabstractProcessing in memory (PiM) represents a promising computing paradigm to enhance performance of numerous dataintensive applications. Variants performing computing directly in emerging nonvolatile memories can deliver very high energy efficiency. PiM architectures directly inherit the vulnerabilities of the underlying memory substrates, but they also are subject to errors due to the computation in place. Numerous well-established error correcting codes (ECC) for memory exist, and are also considered in the PiM context, however, they typically ignore errors that occur throughout computation. In this paper we revisit the error correction design space for nonvolatile PiM, considering both storage/memory and computation-induced errors, surveying several self-checking and homomorphic approaches. We propose several solutions and analyze their complex performance-area-coverage trade-off, using three representative nonvolatile PiM technologies. All of these solutions guarantee single error correction for both, bulk bitwise computations and ordinary memory/storage errors. M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Masoud Zabihi, Yang Lv 0003, Brandon Zink, Jianping Wang 0006, Sachin S. Sapatnekar, Ulya R. Karpuzcu |
ISCA | 6 |