Microcontrollers running safety-critical applications with high integrity requirements must provide appropriate safety measures to manage random hardware faults. For instance, automotive safety regulations (e.g., ISO26262) impose the use of diverse redundancy for items at the highest automotive safety integrity level (ASIL), ASIL-D. In the case of computing cores, this is realized with dual core lockstep (DCLS). The advent of the RISC-VISA has made open source hardware gain popularity. However, there are few industrial open source SoCs meeting the requirements of safety-critical systems, and, to our knowledge, none of them provides lockstep cores. This paper presents the realization of a RISC-V open source lockstep core based on Gaisler's NOEL-V core for the space domain, as well as its integration in the SELENE SoC that provides a complete microcontroller synthesizable on FPGA successfully assessed against space, automotive and railway safety-critical applications in the past.

Nowadays, corrugated packaging is designed and manufactured to provide protection to products and goods when they are shipped. Packaging machinery is being broadly used by manufacturers in cardboard-based packaging production. The results of this machinery are disassembled packaging on pallets. Monitoring these palletized packaging is also recommended to optimize the logistic distribution inside a factory. In this paper, we present a visual monitoring system to perform visual control of palletized packaging workflow. Our system, based on low-cost sensors and deep learning techniques, facilitates the storage in warehouses. Our proposal detects and recognizes different type of cardboard packaging on pallets. Besides, the system counts the pallets of each type for helping to automatically address them on the roller conveyors. We have tested its behavior on a real scenario at Smurfit Kappa facilities as well as evaluated its precision-performance, which reaches an APIoUof 0.93 at 14 FPS using low cost cameras.

RISC-V Instruction Set Architecture (ISA) emerges as an opportunity to develop open source hardware without being subject to expensive licenses or export restrictions. A plethora of initiatives are nowadays developing systems-on-chip (SoCs) and its components based on RISC-V targeting a wide variety of markets. However, domains with safety requirements, such as avionics, space, and automotive, impose SoCs to include support to meet those requirements.This work introduces the SafeX family of components, a set of components providing SoC controllability, observability and safety measures support. These components, developed by the Barcelona Supercomputing Center with permissive open source licenses, are intended to be the basis to make SoCs meet the needs of domains with safety requirements. In particular, the SafeX components developed so far include the SafeSU (multicore statistics unit), the SafeTI (flexible and programmable traffic injector), the SafeDE and SafeSoftDR (hardware and software modules to enforce lockstep execution), and the SafeDM (module to monitor diversity across cores).