Kevin Kai-Chun Chang

dblp:327/1835 · DBLP profile ↗
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5ranked-venue papers
5as first author
5since 2021 · last 2026
0009-0008-4815-2237ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-author · 3 since 2021Software engineering, systems software and programming languages · 2 · 2 first-author · 2 since 2021Artificial intelligence and machine learning · 1 · 1 first-author · 1 since 2021
YearPublicationVenuePosition
2026 ScenicRules: An Autonomous Driving Benchmark with Multi-Objective Specifications and Abstract Scenarios
Kevin Kai-Chun Chang, Ekin Beyazit, Alberto L. Sangiovanni-Vincentelli, Tichakorn Wongpiromsarn, Sanjit A. Seshia
IV1
2024 Dynamic, Multi-objective Specification and Falsification of Autonomous CPS
Kevin Kai-Chun Chang, Kaifei Xu, Edward Kim 0005, Alberto L. Sangiovanni-Vincentelli, Sanjit A. Seshia
RV1
2024 Multi-Corner Timing Macro Modeling With Neural Collaborative Filtering From Recommendation Systems Perspective
abstract
Timing macro modeling has been widely employed to enhance the efficiency and accuracy of parallel and hierarchical timing analysis. However, existing studies primarily focused on generating an accurate and compact timing macro model for single-corner libraries, making it difficult to adapt these approaches to multi-corner situations. This either incurs substantial engineering effort or results in significant performance degradation. To tackle this challenge, we offer a fresh perspective on the timing macro modeling problem by drawing inspiration from recommendation systems and formulating it as a matrix completion task. We propose a neural collaborative filtering-based framework capable of capturing the convoluted relationships between circuit pins and timing corners. This framework enables the precise identification of timing variant regions across different corners. Additionally, we design several training features and implement various training techniques to enhance precision. Experimental results show that our framework reduces model sizes by more than 10% compared to state-of-the-art single-corner approaches, while maintaining competitive timing accuracy and exhibiting significant runtime improvements. Furthermore, when applied to unseen corners, our framework consistently delivers superior performance, demonstrating its potential for use in off-corner chiplets in a heterogeneous integration system.
Kevin Kai-Chun Chang, Guan-Ting Liu, Chun-Yao Chiang, Pei-Yu Lee, Iris Hui-Ru Jiang
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2023 A Safety-Guaranteed Framework for Neural-Network-Based Planners in Connected Vehicles under Communication Disturbance
abstract
Neural-network-based (NN-based) planners have been increasingly used to enhance the performance of planning for autonomous vehicles. However, it is often difficult for NN-based planners to balance efficiency and safety in complicated scenarios, especially under real-world communication disturbance. To tackle this challenge, we present a safety-guaranteed framework for NN-based planners in connected vehicle environments with communication disturbance. Given any NN-based planner with no safety-guarantee, the framework generates a robust compound planner embedding the NN-based planner to ensure overall system safety. Moreover, with the aid of an information filter for imperfect communication and an aggressive approach for the estimation of the unsafe set, the compound planner could achieve similar or better efficiency than the given NN-based planner. A comprehensive case study of unprotected left turn and extensive simulations demonstrate the effectiveness of our framework.
Kevin Kai-Chun Chang, Xiangguo Liu, Chung-Wei Lin, Chao Huang 0015, Qi Zhu 0002
DATE1
2022 Timing macro modeling with graph neural networks
abstract
Due to rapidly growing design complexity, timing macro modeling has been widely adopted to enable hierarchical and parallel timing analysis. The main challenge of timing macro modeling is to identify timing variant pins for achieving high timing accuracy while keeping a compact model size. To tackle this challenge, prior work applied ad-hoc techniques and threshold setting. In this work, we present a novel timing macro modeling approach based on graph neural networks (GNNs). A timing sensitivity metric is proposed to precisely evaluate the influence of each pin on the timing accuracy. Based on the timing sensitivity data and the circuit topology, the GNN model can effectively learn and capture timing variant pins. Experimental results show that our GNN-based framework reduces 10% model sizes while preserving the same timing accuracy as the state-of-the-art. Furthermore, taking common path pessimism removal (CPPR) as an example, the generality and applicability of our framework on various timing analysis models and modes are also validated empirically.
Kevin Kai-Chun Chang, Chun-Yao Chiang, Pei-Yu Lee, Iris Hui-Ru Jiang
DAC1