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Ho Ming Tsui

dblp:327/2070 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2022
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
main memory
0.612022
SMART: on simultaneously marching racetracks to improve the performance of racetrack-based main memory · DAC 2022
Memory systems › emerging memory technologies › spintronic memory
racetrack memory
0.612022
SMART: on simultaneously marching racetracks to improve the performance of racetrack-based main memory · DAC 2022
Memory systems
shift operation reduction
0.612022
SMART: on simultaneously marching racetracks to improve the performance of racetrack-based main memory · DAC 2022

Methods — techniques the papers use, named apart from their topics

simultaneous marching · 0.6proactive scheduling · 0.6
YearPublicationVenuePosition
2022 SMART: on simultaneously marching racetracks to improve the performance of racetrack-based main memory
abstract
RaceTrack Memory (RTM) is a promising media for modern Main Memory subsystems. However, the "shift-before-access" principle, as the nature of RTM, introduces considerable overheads to the access latency. To obtain more insights for the mitigation of shift overheads, this work characterizes and observes that the access patterns, exhibited by the state-of-the-art RTM-based Main Memory, mismatches with the granularity of shift commands (i.e., a group of RaceTracks called Domain Block Cluster (DBC)). Based on the characterization, we propose a novel mechanism called SMART, which simultaneously and proactively marches all DBCs within a subarray, so that subsequent accesses to other DBCs can be served without additional shift commands. Evaluation results show that, averaged across 15 real-world workloads, SMART significantly outperforms other state-of-the-art proposals of RTM-based Main Memory by at least 1.53X in terms of the total execution time, on two different generations of RTM technologies.
Xiangjun Peng, Ming-Chang Yang, Ho Ming Tsui, Chi Ngai Leung, Wang Kang 0001
DAC3