Machine learning (ML) has demonstrated significant promise in various physical design (PD) tasks. However, model generalizability remains limited by the availability of high-quality, largescale training datasets. Creating such datasets is often computationally expensive and constrained by IP. While very few public datasets are available, they are typically static, slow to generate, and require frequent updates. To address these limitations, we present DALI-PD, a scalable framework for generating synthetic layout heatmaps to accelerate ML in PD research. DALI-PD uses a diffusion model to generate diverse layout heatmaps via fast inference in seconds. The heatmaps include power, IR drop, congestion, macro placement, and cell density maps. Using DALI-PD, we created a dataset comprising over 20,000 layout configurations with varying macro counts and placements. These heatmaps closely resemble real layouts and improve ML accuracy on downstream ML tasks such as IR drop or congestion prediction.

VLSI Physical design is a long, stage-coupled flow with multiple tunable parameters. Efficient optimization is challenging because each evaluation is expensive, and decisions made in one stage can strongly affect final metric such as power, performance, and area (PPA). Traditional design space exploration (DSE) methods, such as Bayesian optimization, rely on repeated full-flow evaluations guided by mathematical surrogate models. Although effective in some settings, these methods can be costly and may waste iterations on failed or low-quality configurations.

Over the past year, IEEE CEDA DATC has continued to improve the DATC Robust Design Flow (RDF) while continuing to expand initiatives that advance open infrastructures and culture changes, serving the global community of EDA researchers and users. This invited paper focuses on three highlights: (1) establishment of an accessible, "contrib-like" GitHub resource that provides a more accessible environment for OpenROAD- and OpenROAD-flow-scripts-based research works; (2) the first-ever permission mechanism and benchmarking results for a commercial EDA P&R tool, published with permissions developed with the tool vendor (Siemens EDA); and (3) efforts that support a nascent "ML EDA Commons". The paper also provides brief reviews of the past year’s RDF developments and roadmap updates.

Over the past year, IEEE CEDA DATC has continued to improve the DATC Robust Design Flow (RDF) while also advancing open infrastructure for research, including machine learning for electronic design automation (ML EDA). The 2024 RDF release includes new standalone and integrated global placement and macro placement engines, as well as a CCS-based delay calculator. Advances in baselines and benchmarks include the addition of new benchmarks for macro placement and logic gate sizing, as well as further efforts to establish calibrations of both optimizations and analyses to aid assessments of research progress in EDA. Additional efforts to promote open and reproducible research include refined proxy research enablements and enhanced ML EDA infrastructure through the development and use of new formats, the release of datasets, and the development of Python APIs in OpenROAD.

The electronic design automation (EDA) community has recently begun recognizing the potential of generative artificial intelligence (AI) in chip design. However, its full potential is not fully exploited due to the limited availability of publicly accessible datasets crucial for advancing research in EDA. This paper highlights the dual role of generative AI; in particular, it showcases (i) BeGAN, the use of a generative AI strategy to create thousands of realistic benchmarks for power grid synthesis and analysis to advance power-related research, and (ii) EDA Corpus---an expert-curated and generative AI-enhanced dataset to serve research and development of EDA tool assistants. These two case studies emphasize the ability of generative methods to create and utilize datasets to advance research and lower the barriers to entry in EDA.

Logic gate sizing plays a vital role in timing optimization, especially as Moore's Law slows, shifting greater responsibility to EDA tools to enhance power, performance, and area (PPA), as these gains are no longer achieved solely through scaling and process advancements. There is an increasing need to push the limits of logic gate sizing to extract every possible improvement in PPA. With recent breakthroughs in machine learning (ML) and the computational power of GPUs, there is significant potential to elevate logic gate sizing algorithms to new heights. This contest aims to advance logic gate sizing and push the boundaries of PPA improvement through innovative EDA tools that leverage machine learning and GPU acceleration. As part of the contest, an infrastructure has been developed to enable ML and GPU-accelerated logic gate sizing algorithms, including the release of benchmarks in both standard EDA and ML-friendly formats, along with examples of incorporating "ML inside" EDA tools through Python APIs. The contest leverages the open-source EDA tool OpenROAD and ML-friendly data representation format, CircuitOps, to lower barriers to entry by providing accessible formats and tools, allowing participants to build on existing software without redundancy. With over 25 teams actively participating, the contest highlights growing interest and potential to push the boundaries of timing optimization.

Today's large-scale designs utilize power gating to achieve low power consumption. This strategy involves creating an efficient power switch network that considers both the surge current (inrush) and the time it takes for the domain to wake up (wakeup latency). Optimized design of the power switch network requires an approach that minimizes the inrush current while meeting the wakeup latency specification. However, analyzing the network for inrush is computationally very expensive with large runtimes, particularly for complex networks, making an optimization framework that calls the analysis engine under the hood prohibitively slow. To address this challenge, this paper introduces the use of machine learning (ML) techniques to estimate inrush current. The ML-enabled fast inference for inrush prediction is applied to optimize the power switch network to minimize the inrush current and also meet the wakeup latency constraint. The ML model demonstrates a mean error of 5% compared to SPICE simulations, offering an acceleration of over 50X.

Traditional electronic design automation (EDA) techniques struggle to fulfill the stringent efficiency and quick turnaround demands of complex integrated systems. Machine learning (ML) strategies for EDA (“ML EDA”) are pivotal in transforming EDA to address these challenges. However, they encounter significant obstacles due to inadequate infrastructure, ranging from datasets to software interfaces. This paper demonstrates a software infrastructure for ML EDA built on two key technologies: (i) OpenROAD’s Python APIs, and (ii) NVIDIA’s CircuitOps, an EDA data representation format tailored for ML, facilitating ML EDA applications. The paper illustrates three ML EDA examples that utilize the established OpenROAD and CircuitOps infrastructure.