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Pai Li

dblp:328/8868 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2024
0009-0001-7583-5024ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 70% Hardware accelerators and domain-specific architectures · 30%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization › intermediate representation
intermediate language
0.812024
Unifying Static and Dynamic Intermediate Languages for Accelerator Generators · Proc. ACM Program. Lang. 2024
Electronic design automation › high-level synthesis
accelerator generation
0.812024
Unifying Static and Dynamic Intermediate Languages for Accelerator Generators · Proc. ACM Program. Lang. 2024
Electronic design automation
high-level synthesis
0.812024
Unifying Static and Dynamic Intermediate Languages for Accelerator Generators · Proc. ACM Program. Lang. 2024
Electronic design automation › high-level synthesis › accelerator synthesis
systolic array synthesis
0.212024
Unifying Static and Dynamic Intermediate Languages for Accelerator Generators · Proc. ACM Program. Lang. 2024

Methods — techniques the papers use, named apart from their topics

refinement · 1.5compiler intermediate language design · 1.5
YearPublicationVenuePosition
2024 Unifying Static and Dynamic Intermediate Languages for Accelerator Generators
abstract
Compilers for accelerator design languages (ADLs) translate high-level languages into application-specific hardware. ADL compilers rely on a hardware control interface to compose hardware units. There are two choices: static control, which relies on cycle-level timing; or dynamic control, which uses explicit signalling to avoid depending on timing details. Static control is efficient but brittle; dynamic control incurs hardware costs to support compositional reasoning. Piezo is an ADL compiler that unifies static and dynamic control in a single intermediate language (IL). Its key insight is that the IL’s static fragment is a refinement of its dynamic fragment: static code admits a subset of the run-time behaviors of the dynamic equivalent. Piezo can optimize code by combining facts from static and dynamic submodules, and it opportunistically converts code from dynamic to static control styles. We implement Piezo as an extension to an existing dynamic ADL compiler, Calyx. We use Piezo to implement a frontend for an existing ADL, a systolic array generator, and a packet-scheduling hardware generator to demonstrate its optimizations and the static–dynamic interactions it enables.
Caleb Kim, Pai Li, Anshuman Mohan, Andrew Butt, Adrian Sampson, Rachit Nigam
Proc. ACM Program. Lang.2