The sigmoid function, as a widely used activation function in neural networks, has gained much attention for its approximation and associated usage in edge devices. A recent study applied the Gaussian cumulative function to approximate the sigmoid function. Although this probabilistic method simplifies hardware implementation through a low-complexity binary search, it requires intensive random access memory (RAM) storage, and the search process is time-consuming. Besides, it targets minimizing the maximum mapping error rather than ensuring accurate approximation across all inputs. To address these issues, this article proposes a hardware-friendly and high-accuracy probabilistic-based sigmoid approximator. We first present that given an input, the output of a sigmoid function is strictly equivalent to the probability of a logistic random variable less than or equal to this input. Then, an indirect random variable quantizing strategy is exhibited to reduce memory usage and concurrently minimize precision loss. The latency for the proposed scheme is also optimized. Afterward, a resource-efficient and low-latency sigmoid approximator is developed on digital circuits. Finally, we derive an upper bound on the absolute error between the approximator's output and the true value. Experiments verify the usefulness of our scheme and showcase superior performance in approximation accuracy and resource cost.

In this paper, we demonstrate an energy-efficient real-time object detection and classification system featuring a hybrid event-based frame generation pipeline and a background-removal region proposal algorithm. The event-based frame is generated by aggregating active events within a programmable time interval, generating an event-based binary image (EBBI). This approach enables the utilization of low-complexity algorithms for denoising and object detection. The background-removal region proposal algorithm reduces memory requirements and removes dynamic backgrounds, leading to better detection performance. The proposed system is demonstrated on Zynq-7000 FPGA device with a DAVIS346 sensor. Experimental results show that the proposed system achieves comparable detection accuracy while requiring significantly less computation than existing event-based trackers.

Neuromorphic vision sensors (NVSs) mimic the function of the human visual system, with significant energy-saving potential in IoT-based object detection systems. Unlike conventional sensors, NVSs only generate asynchronous spiking events in response to changes in light intensity. However, the inherent noise generated by NVSs causes a degradation of detection performance. Moreover, an interested object usually occupies only a portion of the entire image frame. Therefore, a real-time, accurate event-based object detection system is needed to identify the region of interest (Rol) and leverage this spatial redundancy to reduce computational load in subsequent recognition modules. In this article, we present an energy-efficient real-time object detection system featuring a hybrid event-based frame generation pipeline and a background-removal region proposal algorithm. The event-based frame is generated by aggregating active events within a programmable time interval, generating an event-based binary image (EBBI). This approach enables the utilization of low-complexity algorithms for denoising and object detection. The background-removal region proposal algorithm reduces memory requirements and removes dynamic backgrounds, leading to better detection performance. The proposed system is demonstrated on Zynq-7000 FPGA device with a DAVIS346 sensor. Experimental results show that the proposed system achieves comparable accuracy while requiring significantly less computation than existing event-based trackers.

Dynamic vision sensors (DVS) have become prevalent in edge vision applications due to their low power and short latency attributes. However, current DVS-based object tracking systems suffer from high power consumption or long processing latency due to high computing intensity of the object detection algorithms. This paper proposes an energy-efficient object detection system through algorithm and hardware co-optimization. We design hardware-efficient denoising and region proposal (RP) algorithms to reduce on-chip memory usage and power consumption. Besides, the processing latency is dramatically reduced thanks to the less computing complexity. The devised algorithm is executed on a heterogeneous platform, with segments particularly sensitive to latency being accelerated via FPGA. An RP processor, supporting both parallel and systolic computing modes, is developed to facilitate the computing-intensive RP generation. Remarkably, the proposed system reduces the on-chip memory by 95.3% in contrast to traditional methods that employ connected component labeling. Moreover, the processing time per frame stands at 92.2 ms, marking a reduction of 82.4% compared to CPU-only operations.

Abstract Software quality is key to the success of software systems. Modern software systems are growing in their worth based on industry needs and becoming more complex, which inevitably increases the possibility of more defects in software systems. Software repairing is time‐consuming, especially locating the source files related to specific software defect reports. To locate defective source files more quickly and accurately, automated software defect location technology is generated and has a huge application value. The existing deep learning‐based software defect location method focuses on extracting the semantic correlation between the source file and the corresponding defect reports. However, the extensive code structure information contained in the source files is ignored. To this end, we propose a software defect location method, namely, multi‐graph learning‐based software defect location (MGSDL). By extracting the program dependency graphs for functions, each source file is converted into a graph bag containing multiple graphs (i.e., multi‐graph). Further, a multi‐graph learning method is proposed, which learns code structure information from multi‐graph to establish the semantic association between source files and software defect reports. Experiments' results on four publicly available datasets, AspectJ, Tomcat, Eclipse UI, and SWT, show that MGSDL improves on average 3.88%, 5.66%, 13.23%, 9.47%, and 3.26% over the competitive methods in five evaluation metrics, rank@10, rank@5, MRR, MAP, and AUC, respectively.

Prior studies have demonstrated that approaches to generate an answer summary for a given technical query in Software Question and Answer (SQA) sites are desired. We find that existing approaches are assessed solely through user studies. Hence, a new user study needs to be performed every time a new approach is introduced; this is time-consuming, slows down the development of the new approach, and results from different user studies may not be comparable to each other. There is a need for a benchmark with ground truth summaries as a complement assessment through user studies. Unfortunately, such a benchmark is non-existent for answer summarization for technical queries from SQA sites.

Semantic code search greatly facilitates software reuse, which enables users to find code snippets highly matching user-specified natural language queries. Due to the rich expressive power of code graphs (e.g., control-flow graph and program dependency graph), both of the two mainstream research works (i.e., multi-modal models and pre-trained models) have attempted to incorporate code graphs for code modelling. However, they still have some limitations: First, there is still much room for improvement in terms of search effectiveness. Second, they have not fully considered the unique features of code graphs.