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Gauri Sharma

dblp:329/8838 · DBLP profile ↗
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2ranked-venue papers
1as first author
2since 2021 · last 2025
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 67% Emerging computing paradigms · 33%
Computer networks
1 paper
Wireless networking · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms
neuromorphic hardware
0.912025
SpikeSpec: An On-Chip Learning Neuromorphic Accelerator for Spectrum Sensing With Triplet-Boosting and Hardware Friendly Loss Function · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
Hardware accelerators and domain-specific architectures › neural network hardware
on-chip learning
0.912025
SpikeSpec: An On-Chip Learning Neuromorphic Accelerator for Spectrum Sensing With Triplet-Boosting and Hardware Friendly Loss Function · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
spiking neural network accelerator
0.912025
SpikeSpec: An On-Chip Learning Neuromorphic Accelerator for Spectrum Sensing With Triplet-Boosting and Hardware Friendly Loss Function · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
Wireless networking › cognitive radio
spectrum sensing
0.312025
SpikeSpec: An On-Chip Learning Neuromorphic Accelerator for Spectrum Sensing With Triplet-Boosting and Hardware Friendly Loss Function · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025

Methods — techniques the papers use, named apart from their topics

triplet-based STDP · 1.7reward-based spike timing-dependent plasticity · 1.7liquid state machine · 1.7hardware-friendly loss function · 1.7
YearPublicationVenuePosition
2025 SpikeSpec: An On-Chip Learning Neuromorphic Accelerator for Spectrum Sensing With Triplet-Boosting and Hardware Friendly Loss Function
abstract
Spectrum sensing (SS) is a pivotal function in next-generation (G) multiple-input-multiple-output (MIMO) communication systems, tasked with detecting and characterizing the occupancy or availability of frequency bands within the radio spectrum. Conventional SS techniques are hindered by challenges, such as hardware complexity and the signal-to-noise ratio (SNR) wall, leading to suboptimal performance in environments with high-noise levels. Recurrent neural networks (RNNs), particularly liquid state machines (LSMs), are highly effective for developing energy-efficient accelerators, as they efficiently capture temporal dependencies in primary user frequency spectrums with a reduced number of trainable parameters. This article introduces an innovative field programmable gate array (FPGA) accelerator based on LSMs, featuring fully integrated on-chip learning capabilities for SS. Our accelerator leverages reward-based spike timing-dependent plasticity (R-STDP) to discern temporal correlations within the related frequency band. Although traditional R-STDP methods face convergence difficulties during on-chip learning, the introduced approach overcomes this challenge with a novel, hardware-efficient loss function. This mechanism which is also hardware friendly, facilitates accelerated convergence with reduction of training period of about 46.67% in SS classification for hardware implementation. Moreover, we implemented a fully asynchronous, low-latency, unsupervised triplet-based spike-time-dependent-plasticity (STDP) learning mechanism in the LSM accelerator reservoir, which improves training accuracy by about 3.88% in high-noise channels while enhancing reconfigurability. Furthermore, we investigated various encoder mechanisms to identify the most efficient encoder architecture for our LSM, leading to an accuracy increase of 6.11%. Our optimized LSM architecture achieved 1.27 times and 2.01 times the LUT and register counts, respectively, compared to the basic fixed-reservoir LSM on the Virtex-707 FPGA.
Muhammad Farhan Azmine, Ruizhe Li 0006, Gauri Sharma, Yang Yi 0002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
2024 Unveiling vulnerabilities: evading YOLOv5 object detection through adversarial perturbations and steganography
Gauri Sharma, Urvashi Garg
Multim. Tools Appl.1