Higher-order staircase codes form a class of generalized staircase codes in which each bit is protected by more than two component codes. Among them, the extended-Hamming-based higher-order staircase codes are promising candidates for applications that require high coding rate, low error floor, and low decoding complexity. Despite their potential, their performance is still limited by conventional decoding methods, and the structural properties of their minimum stall patterns are not fully understood. To address these issues, we first introduce a novel soft-aided bounded distance decoder (SA-BDD) based on constrained bit flipping (CBF), denoted as SA-BDD-CBF, which demonstrates an effective performance–complexity–latency tradeoff of the extended-Hamming-based higher-order staircase codes. With appropriate parameter, the complexity of SA-BDDCBF is at most 3.4 times that of BDD. This is significantly lower than those of the multiply-chained zipper code and the traditional staircase code, which require approximately 31 and 39 times the complexity of BDD, respectively. Meanwhile, its performance gaps to the comparable multiply-chained zipper code and the traditional staircase code is only 0.10–0.15 dB, demonstrating an effective trade-off between decoding complexity and performance. We then establish several properties of the stall patterns and leverage these properties to develop efficient algorithms to search for both intra- and inter-block stall patterns. These algorithms provide exact values or upper bounds on the minimum sizes of the stall patterns. Extensive simulation results confirm the advantages of the proposed SA-BDD-CBF. In particular, it achieves a gain of 0.4 dB, while the associated increase in complexity remains acceptable for practical deployment. Moreover, the searching algorithms determine the exact minimum sizes of the stall patterns for block sizes up to 10 and obtain upper bounds for block sizes larger than 10. These findings advance the practical deployment of higher-order staircase codes in future high-throughput communication systems.

In the industrial Internet of Things (IIoT), edge computing is a pivotal power in enhancing system efficiency and responsiveness. However, traditional edge computing faces some challenges like poor flexibility in communication and susceptibility to blockages. Autonomous aerial vehicles (AAVs)-assisted edge computing can address these challenges due to their flexible deployment and strong Line of Sight (LoS) link capabilities. But it also confronts challenges like signal attenuation and resource constraints. To solve these problems, reconfigurable intelligent surface (RIS) emerges as a promising integration strategy to enhance network communication and computing capabilities. Integrating AAVs and RISs in complex dynamic edge computing system poses a notable challenge in achieving real-time and efficient decision-making. Digital twin (DT) technology is an advanced technology that establishes real-time mapping and interaction between the physical world and virtual models, thereby providing real-time status monitoring and precise offloading decisions for the system. Therefore, this article considers a novel DT-driven edge computing system supported by AAVs equipped with RIS in IIoT. In this system, we focus on the intelligent computation offloading problem, whose objective is to minimize the maximum execution time across all user devices (UDs). To tackle this nonconvex mixed-integer nonlinear optimization problem, we decompose it into the scheduling and offloading optimization problem and the allocation optimization problem. Then, we first propose a multitask reinforcement learning algorithm to solve the scheduling and offloading optimization problem by optimizing the AAV trajectories, UD offloading choices, and RIS phase shifts. Afterward, based on the solution of the scheduling and offloading optimization problem, we propose an alternating iterative algorithm to address the allocation optimization problem through optimizing the offloading ratio and resource allocation. Finally, through extensive simulation experiments, we validate the effectiveness and feasibility of our proposed solution.

Product-like codes are widely used in high-speed communication systems since they can be decoded with low-complexity hard decision decoders (HDDs). To meet the growing demand of data rates, enhanced HDDs are required. In this paper, we propose a novel soft-aided HDD (SA-HDD), termed iterative bounded distance decoding with random flipping (iBDD-RF), for product-like codes. In iBDD-RF, the soft reliability of a bit is a weighted sum of the output of bounded distance decoder (BDD) and the channel log-likelihood ratio (LLR). When the amplitude of the soft reliability of a bit is less than a given threshold, it is flipped with a given probability. This random flipping may make the decoder escape from the local optimum. To optimize the threshold and the flipping probability, we derive the density evolution (DE) equations of iBDD-RF for product codes (PCs) and staircase codes (SCs). Our extensive numerical results show that iBDD-RF outperforms iBDD with scaled reliability (iBDD-SR) over the binary-input additive white Gaussian noise (Bi-AWGN) channel. Particularly, for a PC with (255,239,2) Bose-Chaudhuri-Hocquenghem (BCH) code and an SC with (254,230,3) BCH code, iBDD-RF performs about 0.25 dB and 0.28 dB better than iBDD-SR, respectively.

Cyclic redundancy check-aided tail-biting convolutional code (CRC-TBCC) is considered as a competitive candidate for ultra-reliable and low-latency communications (URLLC) in short-length transmission scenarios. This paper focuses on designing efficient list decoders for CRC-TBCC and constructing rate-compatible CRC-TBCC (RC-CRC-TBCC). To reduce decoding complexity, we introduce a serial list Viterbi algorithm (SLVA) based on sectionalized trellises (ST), referred to as ST-SLVA. Comparative analysis reveals that ST-SLVA significantly lowers the decoding complexity. We then propose to use selectively multiplicative repetition (SMR) to construct high-performance rate-compatible CRC-TBCC. The resulting family of codes, called SMR-CRC-TBCCs, can be decoded with the same ST-SLVA. In SMR-CRC-TBCC, adjacent coded bits of CRC-TBCC are treated as symbols of a given finite field for multiplicative repetition, with priority given to the repetition of CRC-related symbols. Simulation results demonstrate that SMR-CRC-TBCC delivers excellent performance across various coding rates. Particularly, it performs better than CRC-aided Polar (CA-Polar) codes, LTE-Turbo codes, and parallel concatenated convolutional-block (PCCB) codes. These results strengthen the competitiveness of CRC-TBCC for 6G short-length communications.

Vehicular edge computing (VEC) is an efficient solution to alleviate the limitations of local computing resources in vehicular networks. However, the high mobility of vehicles and the dynamic variability of network topologies make it significantly challengeable. In this work, we make a fusion of model-driven and data-driven intelligence to design a multi-agent deep reinforcement learning (DRL) solution for task offloading in urban VEC networks. First, computational models for task queue, transmission, computation, energy consumption, and expense are meticulously developed for the VEC network that integrates communication and computation. Vehicular tasks vary in type, urgency, size, and timeframe, leading to different latency requirements. Tasks may be executed locally within the vehicle, at a server after V2I offloading via cellular communications, or in a neighboring vehicle after V2V offloading via millimeter-wave (mmWave) communications. Each of these options incurs different levels of latency, energy consumption, and expense. Second, based on these models and the utility function that combines latency, energy consumption, and expense, an optimization problem for task offloading is formulated. This problem can be interpreted as a Markov decision process with a carefully designed reward function. Third, to address the offloading problem, we propose a multi-agent proximal policy optimization-based task and target selection algorithm (MAPPO-TTSA). This algorithm also utilizes convolutional neural networks to extract features from large-scale states, thereby enhancing their correlation. Fourth, comprehensive training is performed on the observational data to determine the optimal parameters for predicting task offloading. Finally, extensive experiments are conducted, and simulation results are provided to demonstrate that the proposed intelligent task offloading scheme offers significant advantages in terms of average task completion delay and utility level across various scenarios.

Product codes (PCs) are typically decoded using iterative bounded distance decoding (iBDD) to ensure a low decoding complexity. To obtain further performance gain, a soft-aided decoding algorithm, termed the iBDD with scaled reliability (iBDD-SR), was proposed for PCs. In this paper, we propose an enhanced iBDD-SR by introducing threshold and memory when passing messages between the component decoders. The resulting algorithm is referred to as the threshold-based binary message passing (TB-BMP) with memory. In the proposed decoding algorithm, the soft reliability of the BDD output at the current half-iteration is a weighted sum of the BDD output, the channel reliability, and the content of the memory unit, where the content of the memory unit at the current half-iteration is related to the selected threshold and the BDD output at last half-iteration. Due to the existence of memory, the Bayesian network is used to model the decoding process of the TB-BMP. Based on the Bayesian network, we derive the density evolution (DE) equations for the TB-BMP under the constraint of extrinsic message passing (EMP). The analytical results of the DE analysis can be used to guide the selection of the parameters of the TB-BMP decoder. Extensive simulation results show that the TB-BMP decoder outperforms the iBDD-SR over the binary-input additive white Gaussian noise (Bi-AWGN) channels. In particular, for a PC based on a two-error-correcting extended Bose-Chaudhuri-Hocquenghem (BCH) code of length 256, the TB-BMP decoder performs about 0.28 dB better than the iBDD-SR at a bit error rate (BER) of 10-7.

As subclasses of spatially coupled turbo-like codes (SC-TCs), hybrid coupled serially concatenated codes (HC-SCCs) and spatially coupled serially concatenated codes (SC-SCCs) are attractive for streaming applications. However, it is a long-standing problem to estimate the error floors of HC-SCCs and SC-SCCs. To tackle this problem, we present a genie-aided approach in this paper. Specifically, we first show that the performance of a given HC-SCC or SC-SCC can be lower bounded by a hybrid concatenated code which is obtained by assuming the coupled sub-sequences are known or partially known. Second, we derive the average input-output weight enumerating functions (IOWEF) of the hybrid concatenated code ensembles corresponding to SC-SCC and HC-SCC. Third, the obtained IOWEFs are used to estimate the error floors. The numerical results show the tightness of the proposed method in estimating the error floors of SC-SCCs and HC-SCCs. We then use the proposed method to analyze the impact of the memories of the component convolutional codes on error floor. Particularly, we show that, for a given total memory order$v$, the lowest error floor is achieved by selecting the memories of the outer and inner component convolutional codes as$\lceil \frac {v}{2} \rceil $and$\lfloor \frac {v}{2} \rfloor $, respectively. In addition, for both SC-SCCs and HC-SCCs, reduced error floor can be achieved by increasing the outer coupling memory.

Constructions of high-performance hard-decision decodable error correction codes are important for high-speed communication systems. In this paper, we present the generalized integrated interleaved (GII) zipper codes, in which multiple zipper codes are coupled together by the constraint of the GII code. The resulting codes are referred to as GII-zipper codes. Firstly, since the performances of GII-zipper codes are sensible to miscorrections, we propose an enhanced anchor decoder (AD) which uses the hard-decision results during the GII decoding to assign anchor reliability to reduce miscorrections. We then analyze the size and multiplicity of the minimum-sized stall patterns (MSSPs) of the GII-zipper codes. The analytical results show that the size of the MSSPs of the GII-zipper codes is larger that of the zipper codes. Finally, we present extensive simulation results to show the performance advantages of the GII-zipper codes. The results show that, when decoded with the original AD, the GII-zipper codes perform better than the comparable zipper codes and we can obtain further performance gain by the enhanced AD. Particularly, a GII-staircase code with a rate of 0.846 can achieve 0.74 dB from capacity at a bit error rate (BER) of 10−15.

In this paper, we present a class of hybrid coupled serially concatenated codes (HC-SCC), in which coupling is achieved by re-encoding partial outputs from both the outer and the inner encoders. Firstly, we derive the exact density evolution (DE) equations over the binary erasure channels (BECs) for the HC-SCCs, which can be used to analyze the impact of the coupling ratios and the coupling memories on the performances of the HC-SCCs. Secondly, we present a genie-aided lower bound for the proposed HC-SCCs to estimate their error-floors. Thirdly, we use the DE equations to design randomly punctured HC-SCCs, including rate-compatible HC-SCCs. The analytical and the numerical results show that: 1) for comparable coupling memories, the iterative decoding thresholds of the proposed HC-SCC ensembles are better than those of the recently introduced spatially coupled serially concatenated code (SC-SCC) ensembles and the partially parity-coupled turbo code (PPC-TC) ensembles; 2) with outer coupling memory five and inner coupling memory five, the iterative decoding thresholds of the rate-compatible HC-SCCs over the BECs are 0.0003 away from the corresponding channel capacities for a wide range of coding rates; 3) simulation results over the additive white Gaussian noise (AWGN) channels and the BECs are provided to confirm the performance advantages of the HC-SCCs. Particularly, the simulation results show that the HC-SCCs admit lower error-floor than the SC-SCCs and the rate-compatible HC-SCCs perform better than the PPC-TCs, which are consistent with the results of DE analysis.

Tiled diagonal zipper codes (TDZCs) are shown to be a class of competitive forward error correction codes in modern optical fiber communication systems. This paper introduces the multichain tiled diagonal zipper codes (MC-TDZCs) in which multiple TDZC chains are coupled together in a cyclic manner. Firstly, we present the encoding and decoding algorithms of the proposed MC-TDZCs. Secondly, we analyze the graphical structures of the minimum stall patterns of the MC-TDZCs using directed graphs. Thirdly, we derive the multiplicities of these minimum stall patterns. The analytical results show that the size of the minimum-sized stall patterns of the proposed MC-TDZCs is larger than that of the underlying TDZC counterpart. Finally, we present simulation results to show the performance advantages of the proposed MC-TDZCs under the constraint of equal storage size for decoding. Particularly, a rate 0.94 MC-TDZC with four chains shows more than four orders of magnitude improvement in bit error rates compared to its underlying TDZC counterpart.

In this paper, we formulate the problem to cope with the transmission of extra bits over an existing coded transmission link (referred to as coded payload link) without any cost of extra transmission energy or extra bandwidth. This is possible since a gap to the channel capacity typically exists for a practical code. A new concept, termed asaccessible capacity, is introduced to specify the maximum rate at which the superposition transmission of extra bits is reliable and has a negligible effect on the performance of the coded payload link. For a binary-input output-symmetric (BIOS) memoryless channel, the accessible capacity can be characterized as the difference between the channel capacity and the mutual information rate of the coded payload link, which can be numerically evaluated for very short payload codes. For a general payload code, we present a simple lower bound on the accessible capacity, given by the channel capacity minus the coding rate of the payload code. We then focus on the scenarios where low-density parity-check (LDPC) codes are implemented for the payload link. We propose to transmit extra bits by random superposition for encoding, and exhaustive search (with the aid of statistical learning) for decoding. We further propose, by establishing an auxiliary channel (calledsyndrome channel) induced from “zero-forcing” over the binary field, to transmit extra bits with structured codes such as repetition codes and first-order Reed-Muller (RM) codes. Numerical results show that up to 60 extra bits can be reliably transmitted along with a rate-1/2 LDPC code of length 8064.

Content-sharing is one of the major applications of vehicular networks. To fully utilize the spectrum and the connection time, rate-compatible codes are required when sharing content. In this paper, we present a simple and flexible method to construct low-complexity rate-compatible codes for content sharing. We first present a novel construction framework for rate-compatible codes via recursive block Markov superposition transmission (rBMST). In the proposed construction, the shared content is partitioned into equal-length data chunks and transmitted directly, while their replicas are taken as the inputs of a given number of parallel systematic encoders to generate parity-check chunks. These parity-check chunks are then transmitted in parallel in a recursive block Markov superposition transmission manner. The proposed construction is flexible in the sense that codes with arbitrary rates can be obtained by adjusting the number of parallel rBMST encoders and the number of randomly punctured bits. We show that the simplest construction, using repetition to generate the parity-check chunks, leads to high-performance and low-complexity rate-compatible rBMST (RC-rBMST) codes. Specifically, the extrinsic information transfer (EXIT) chart analysis shows that asymptotic thresholds of the repetition-based RC-rBMST (RB-RC-rBMST) codes are within 0.25 dB of the channel capacities for a wide range of coding rates. Numerical results are presented to confirm the advantages of the RB-RC-rBMST codes in performance and complexity. Particularly, the RB-RC-rBMST codes perform as well as BMST-R codes but with much lower computational complexities.

In this paper, we introduce a novel method, called doubly-recursive block Markov superposition transmission (DrBMST), to construct high-performance spatially coupled codes. An important characteristic of DrBMST codes is that the degrees of the constraint nodes in their normal graphs are at most three. As a result, DrBMST codes can be decoded with low complexity. We first prove that the error probability of an enlarged DrBMST code ensemble can be made arbitrarily small under windowed maximum-likelihood decoding (MLD) by increasing the decoding window size. This result partially explains the superior performances of DrBMST codes. Then we propose to use the extrinsic information transfer (EXIT) chart analysis to estimate the iterative windowed decoding thresholds of DrBMST codes. The EXIT chart analyses show that, with such a simple structure, DrBMST codes are comparable to BMST codes with large encoding memories in terms of decoding thresholds. Finally, we carry out comparisons to validate the advantages of DrBMST codes in terms of error performances and decoding complexities. In particular, for a decoding latency of 20,000 bits, the DrBMST code performs better than the (4, 8)-regular spatially coupled low-density parity-check (SC-LDPC) code, but with lower computational complexity. Hence, DrBMST codes can be used in communication systems with limited computational resources. In addition, we show that DrBMST can be used to construct multiple-rate codes.

For industrial Internet of Things (IIoT), data trustworthiness should be maintained both at the time of sensing and at the time of transmission. This article is concerned with trustworthiness during transmission, which is determined by transmission reliability. We present a low-complexity and flexible method via partial and recursive superposition to improve the transmission reliability of IIoT, resulting in an IIoT with high trustworthiness. In our method, a portion of the previously transmitted data are superimposed onto the current transmitted data to introduce memory among different transmissions, which are then exploited by the windowed decoder to obtain performance gain. The proposed method is referred to as partially recursive block Markov superposition transmission of low-density parity-check (PrBMST-LDPC) codes. This article is focused on the construction of low-complexity PrBMST-LDPC codes since IIoT is resource-limited in nature. The first construction is the memory-one PrBMST-LDPC code. We present a simplified density evolution algorithm to optimize the superposition ratio for memory-one PrBMST-LDPC code. Both the analytical and numerical results show that PrBMST with memory one can be used to reduce the packet loss ratio (PLR) of IIoT using LDPC codes. Particularly, around 1.0 dB performance gain is obtained by PrBMST. We then present a low-complexity construction for PrBMST-LDPC codes with encoding memory larger than one. Simulation results show that compared with memory-one PrBMST, a further PLR reduction of around one order of magnitude can be obtained.

In this paper, we introduce the doubly recursive block Markov superposition transmission (DrBMST) of short code. An important characteristic of DrBMST codes is that the degrees of the constraint nodes in their normal graphical realizations are at most three. As a result, DrBMST codes can be decoded with low complexity. We propose to use an enlarged code ensemble to analyze the performance of DrBMST under windowed maximum likelihood decoding. Further, the extrinsic information transfer (EXIT) chart analysis is used to study the iterative decoding thresholds of DrBMST code ensembles. The EXIT analysis shows that the iterative decoding thresholds of DrBMST code ensembles are comparable to those of the BMST codes. We have also compared the error performance and the decoding complexity of finite-length DrBMST codes with regular spatial-coupled low-density parity-check (SC-LDPC) codes under equal decoding latency. The comparison results show that the DrBMST code performs about 0.1 dB better than a (4, 8)-regular SC-LDPC code, but with lower computational complexity.

Extensive studies have demonstrated the effectiveness and the flexibility of constructing capacity-approaching codes by block Markov superposition transmission (BMST). However, to achieve high performance, BMST codes typically require large encoding memories and large decoding window sizes, which result in high decoding complexity and high decoding latency. To address these issues, we introduce the recursive BMST (rBMST), in which the block-oriented feedback convolutional code is used instead of the block-oriented feedforward convolutional code of BMST. We propose to use a modified extrinsic information transfer chart analysis, which relates the mutual information to the bit error rate, to study the convergence behaviors of rBMST codes. On one hand, rBMST code shares most merits of BMST code, including near-capacity performance, low-complexity encoding, and flexible construction. On the other hand, compared with BMST code, rBMST code requires a smaller encoding memory, hence a lower decoding complexity, to approach the capacity. In particular, both analytical and simulation results show that rBMST code with encoding memory three reveals a lower error floor than the BMST code with encoding memory twelve. Furthermore, we show by analysis and simulations that rBMST with fixed encoding memory (m = 3 ) and fixed decoding delay (d = 12 ) can be used to construct capacity-approaching multiple-rate codes. Finally, the comparison between rBMST codes and spatially coupled low-density parity-check codes is carried out, which shows the advantages of rBMST codes in terms of performances and decoding complexities.

Extensive studies have demonstrated the effectiveness of constructing capacity-approaching codes by block Markov superposition transmission (BMST). However, to achieve high performance, BMST codes typically require large encoding memories and large decoding window sizes, which result in increased decoding complexity and decoding latency. To address this issue, we introduce the recursive BMST (rBMST), in which block-oriented feedback convolutional code is used instead of the block-oriented feedforward convolutional code. We propose to use a modified extrinsic information transfer (EXIT) chart analysis to study the convergence behavior of rBMST codes. On one hand, rBMST code shares most merits of BMST code, including near-capacity performance, low-complexity encoding, and flexible construction. On the other hand, compared with BMST code, rBMST code requires a smaller encoding memory, hence a lower decoding complexity, to approach the capacity. In particular, analytical results show that, rBMST code ensemble with encoding memory three reveals a lower error-floor than the BMST code ensemble with encoding memory twelve.

Structural properties of array-based non-binary low-density parity-check (NBLDPC) codes are studied in this paper. First, we characterize graphical substructures induced by codewords of symbol weight six in array-based NBLDPC codes defined by parity-check matrices with column weight three. We also reveal necessary conditions for these graphical substructures to incur weight-6 codewords. Such conditions can be used to select nonzero elements for avoiding weight-6 codewords or reducing the multiplicity of weight-6 codewords. Second, we show that there exist weight-7 codewords in array-based NBLDPC codes defined by parity-check matrices with column weight three. As a byproduct, we find that the graphical substructure induced by a weight-7 codeword takes the graphical substructure induced by the related weight-6 codewords as a subgraph. Third, we show that there may exist codewords with symbol weight four, six, and seven in array-based NBLDPC codes defined by parity-check matrices with column weight two. These results enrich the structural analysis of array-based LDPC codes. In addition, simulation results show the performance advantage of array-based NBLDPC codes.

This paper studies the transmission of Gaussian sources through additive white Gaussian noise channels in bandwidth expansion regime, i.e., the channel bandwidth is greater than the source bandwidth. To mitigate the error propagation phenomenon of conventional digital transmission schemes, we propose in this paper a new capacity-approaching joint source channel coding (JSCC) scheme based on partially block Markov superposition transmission (BMST) of nested lattice codes. In the proposed scheme, first, the Gaussian source sequence is discretized by a lattice-based quantizer, resulting in a sequence of lattice points. Second, these lattice points are encoded by a short systematic group code. Third, the coded sequence is partitioned into blocks of equal length and then transmitted in the BMST manner. The main characteristics of the proposed JSCC scheme include: 1) entropy coding is not used explicitly and 2) only parity-check sequence is superimposed, hence, termed partially BMST. This is different from the original BMST. To show the superior performance of the proposed scheme, we present extensive simulation results which show that the proposed scheme performs within 1 dB of the Shannon limits. Hence, the proposed scheme provides an attractive candidate for transmission of Gaussian sources.

In this paper, we analyze and optimize non- binary low-density parity-check (NB-LDPC) codes for magnetic recording applications. While the topic of the error floor performance of binary LDPC codes over additive white Gaussian noise (AWGN) channels has recently received considerable attention, very little is known about the error floor performance of NB-LDPC codes over other types of channels, despite the early results demonstrating superior characteristics of NB-LDPC codes relative to their binary counterparts. We first show that, due to outer looping between detector and decoder in the receiver, the error profile of NB-LDPC codes over partial-response (PR) channels is qualitatively different from the error profile over AWGN channels - this observation motivates us to introduce new combinatorial definitions aimed at capturing decoding errors that dominate PR channel error floor region. We call these errors (or objects) balanced absorbing sets (BASs), which are viewed as a special subclass of previously introduced absorbing sets (ASs). Additionally, we prove that due to the more restrictive definition of BASs (relative to the more general class of ASs), an additional degree of freedom can be exploited in code design for PR channels. We then demonstrate that the proposed code optimization aimed at removing dominant BASs offers improvements in the frame error rate (FER) in the error floor region by up to 2.5 orders of magnitude over the uninformed designs. Our code optimization technique carefully yet provably removes BASs from the code while preserving its overall structure (node degree, quasi-cyclic property, regularity, etc.). The resulting codes outperform existing binary and NB-LDPC solutions for PR channels by about 2.5 and 1.5 orders of magnitude, respectively.

In this study, the authors present a low‐complexity iterative joint detection–decoding algorithm for majority‐logic decodable non‐binary low‐density parity‐check (LDPC) coded modulation systems. In the proposed algorithm, a hard‐in–hard‐out decoder is combined with a hard‐decision signal detector in an iterative manner. Each iteration consists of five phases. Firstly, the detector makes hard decisions based on the iteratively updated ‘received’ signals; secondly, these hard decisions are distributed via variable nodes to check nodes; thirdly, check nodes compute hard extrinsic messages; fourthly, each variable node counts hard extrinsic messages from its adjacent check nodes and feeds back to the detection node the symbol with the most votes as well as the difference between the most votes and the second most votes; finally, these feedbacks are used to shift each ‘received’ signal point along an estimated direction to possibly reduce noise. The proposed algorithm requires only integer operations and finite field operations and consequently can be implemented with simple combinational logic circuits in practical systems. Simulation results show that the proposed algorithm performs well and hence serves as an attractive candidate for trading off performance against complexity for majority‐logic decodable non‐binary LDPC codes.

This study is concerned with the application of non‐binary low‐density parity‐check (NB‐LDPC) codes to binary input inter‐symbol interference channels. Two low‐complexity joint detection/decoding algorithms are proposed. One is referred to as max‐log‐MAP/X‐EMS algorithm, which is implemented by exchanging soft messages between the max‐log‐MAP detector and the extended min‐sum (EMS) decoder. The max‐log‐MAP/ X ‐EMS algorithm is applicable to general NB‐LDPC codes. The other one, referred to as Viterbi/GMLGD algorithm, is designed in particular for majority‐logic decodable NB‐LDPC codes. The Viterbi/GMLGD algorithm works in an iterative manner by exchanging hard‐decisions between the Viterbi detector and the generalised majority‐logic decoder (GMLGD). As a by‐product, a variant of the original EMS algorithm is proposed, which is referred to as µ ‐EMS algorithm. In the µ ‐EMS algorithm, the messages are truncated according to an adaptive threshold, resulting in a more efficient algorithm. Simulations results show that the max‐log‐MAP/ X ‐EMS algorithm performs as well as the traditional iterative detection/decoding algorithm based on the BCJR algorithm and theQ‐ary sum–product algorithm, but with lower complexity. The complexity can be further reduced for majority‐logic decodable NB‐LDPC codes by executing the Viterbi/GMLGD algorithm with a performance degradation within one dB. These algorithms provide good candidates for trade‐offs between performance and complexity.

This letter is concerned with a class of nonbinary low-density parity-check (LDPC) codes, referred to as column-scaled LDPC (CS-LDPC) codes, whose parity-check matrices have a property that each column is a scaled binary vector. The CS-LDPC codes, which include algebraically constructed nonbinary LDPC codes as subclasses, admit fast encoding and decoding algorithms. Specifically, for a code over the finite field F2p, the encoder can be implemented with p parallel binary LDPC encoders followed by a series of bijective mappers, while the decoder can be implemented with an iterative decoder in which no message permutations are required during the iterations. In addition, there exist low-complexity iterative multistage decoders that can be utilized to trade off the performance against the complexity. Simulation results show that the performance degradation caused by the iterative multistage decoding algorithms is relevant to the code structure.

In this paper, we presented three approaches to improve the design of Kite codes (newly proposed rateless codes), resulting in an ensemble of rate-compatible LDPC codes with code rates varying “continuously” from 0.1 to 0.9 for additive white Gaussian noise (AWGN) channels. The new ensemble rate-compatible LDPC codes can be constructed conveniently with an empirical formula. Simulation results show that, when applied to incremental redundancy hybrid automatic repeat request (IR-HARQ) system, the constructed codes (with higher order modulation) perform well in a wide range of signal-to-noise-ratios (SNRs).

Kite codes, which were originally defined over the binary field, are generalized to arbitrary abelian groups in this paper. Kite codes are a special class of prefix rateless codes over groups, which can generate potentially infinite (or as many as required) random-like parity-check symbols. In this paper, we consider four kinds of Kite codes, which are binary Kite codes, Kite codes over one-dimensional lattices, Kite codes over M-PSK signal constellations and Kite codes over multi-dimensional lattices. It is shown by simulations that the proposed codes perform well over additive white Gaussian noise channels.