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T. Kure

dblp:33/2875 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › technology computer-aided design
process simulation
0.011987
A Two-Dimensional Etching Profile Simulator: ESPRIT · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987
Electronic design automation › semiconductor manufacturing
lithographic patterning
0.011987
A Two-Dimensional Etching Profile Simulator: ESPRIT · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987

Methods — techniques the papers use, named apart from their topics

string model · 0.0
YearPublicationVenuePosition
1987 A Two-Dimensional Etching Profile Simulator: ESPRIT
abstract
A two-dimensional etching simulator named ESPRIT (FOOTNOTE: ESPRIT--Etching Simulation PRogram with an Improved sTring model.) has been developed to simulate LSI patterning. The etching simulator includes isotropic and anisotropic components. Its calculation method is based on the string model. ESPRIT can simulate etched profiles for multilayers with different etching rates and calculate side etching using sloped incidental anisotropic components. In addition, location correction, loop elimination, point insertion, and point elimination are provided for stable and accurate calculations. Simulated profiles coincide well with those from experiments in terms of relationship between the groove width and etched depth. ESPRIT can support to design LSI patterning process.
Shuichi Yamamoto, T. Kure, Masanori Ohgo, Teruo Matsuzawa, S. Tachi, Hideo Sunami
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2