The programming of the AnyBoard is demonstrated by the design of a digital oscilloscope. The operations needed to enter, simulate, store, map, and debug a design are designed. The length of time needed to accomplish each of these operations is used to justify some proposed enhancements to the AnyBoard rapid-prototyping environment.>

We derive the learning theory recently reported by Tishby, Levin, and Solla (TLS) directly from the principle of maximum entropy instead of statistical mechanics. The theory generally applies to any problem of modeling data. We analyze an elementary example for which we find the predictions consistent with intuition and conventional statistical results and we numerically examine the more realistic problem of training a competitive net to learn a one-dimensional probability density from samples. The TLS theory is useful for predicting average training behavior.

A massively parallel, all-digital, stochastic architecture-TInMANN-that acts as a Kohonen self-organizing feature map is described. A VLSI design is shown for a TInMANN neuron which fits within a small, inexpensive MOSIS TinyChip frame, yet which can be configured to build networks of arbitrary size. The neuron operates at a speed of 15 MHz, making it capable of processing 195000 three-dimensional training examples per second. Three man-months were required to synthesize the neuron and its associated level-sensitive scan logic using the OASIS silicon compiler. The ease of synthesis allowed many performance trade-offs to be examined, while the automatic testability features of the compiler helped the designers achieve 100% fault coverage of the chip. These factors served served to create a fast, dense, and reliable neural chip.

A technique for adaptive filtering of nonlinear systems with memory has been developed which combines quantized mean field annealing (QMFA) and conventional recursive-least-squares/fast-transversal filter (RLS/FTF) adaptive filtering. Unlike other methods which rely on Volterra and Wiener models, this technique can efficiently handle large order nonlinearities with or without memory. The nonlinear channel is divided into a memory nonlinearity followed by a dispersive linear system. Assuming that the dispersive linear system is stationary during initialization and the nonlinearity does not change while the dispersive linear system varies with time, QMFA is applied to obtain the coefficients and the order of the memory of the nonlinearity and RLS/FTF is applied to determine the weights of the dispersive linear system. This method was applied to a full duplex digital subscriber loop. Simulations show that the performance of the technique is superior to that of ordinary RLS/FTF and steepest descent algorithms.>

A technique is presented for finding transmitter and receiver filters for a wide class of data transmission systems which minimize the bit error rate (BER). The techniques uses Monte Carlo simulation to estimate the BER, coupled with mean field annealing (MFA) to optimize the pulse shapes. Modeling of the link can be as complex as simulation will allow, while MFA is resistant to the statistical scatter in the BER estimate from the simulation. In a complex example, MFA is coupled with Monte Carlo simulation techniques to find near optimal transmit and receive filters for a satellite communications link, taking 6 CPU hours on a DECstation 3100. The bit error rate of the link is found to be as much as three orders of magnitude lower when using the MFA-constructed optimal filters than when using filters constructed by gradient descent and simulated annealing.>

The authors introduce the use of logical consequences in determining cost functions for neural networks which solve optimization or constraint-satisfaction problems. This technique estimates the changes required in the remaining neuron outputs in order to maintain a valid solution when a selected neuron is forced on or off. From this estimate, an estimate can be made of the cost change due to the change in the selected neuron. The set of estimated costs for all the neurons is then used to update their respective outputs. Applying logical consequences in some problems eliminates the need to use penalty functions to transform constrained problems into unconstrained problems suitable for solution by neural nets. The neural nets derived with this technique nearly always produced valid solutions to the traveling salesman problem, and the solutions were only 5% above the best solutions found using simulated annealing. Graph bipartitioning was also performed, but the percentage of balanced solutions fell into the 70% to 90% range due to a violation of one of the implicit assumptions in the model

A 100000-transistor digital CMOS Hopfield neural network is presented, and its performance is discussed. STONN uses space efficient stochastic logic and bitwise pipelining to achieve massive parallelism and high operational speeds. The architecture produces solutions to optimization problems with a quality equivalent to that of solutions produced by analog networks and nearly as good as those found using simulated annealing. The massively parallel nature of STONN increases its speed of convergence by orders of magnitude over uniprocessor implementations. The completely digital STONN design provides dynamically reprogrammable parameters and a practical system implementation which can be expanded using several identical chips

A rapid prototyping system for teaching digital design is described. The system uses electronically-reconfigurable field programmable gate arrays (FPGAs) to implement a specific logic design without requiring any physical changes to the prototyping system. The user specifies designs using a text based description language. The prototyping system partitions the input logic among the available FPGA resources while observing constraints on gate density and chip I/O. The combinational logic blocks (CLBs) in each individual FPGA are then placed and the interconnections are routed. Once programmed, the system can be exercised using a pattern generator and logic analyzer. The Anyboard system reduces the time required to implement a design and avoids some of the problems associated with the use of wire-wrap or prototyping board implementations.>

A technique for finding transmitter and receiver filters for a wide class of digital communication systems which minimize the bit-error rate (BER) is presented. The technique uses Monte Carlo simulation to estimate the BER and mean field annealing (MFA) to optimize the pulse shapes. Modeling of the link can be as complex as simulation will allow, while MFA is resistant to the statistical variation in the BER estimate from the simulation. Initially, the MFA technique was applied to a binary symmetric channel in a nonsimulation environment, and an approximate analysis of the behavior of MFA for this problem was performed. In a more complex example, MFA was coupled with Monte Carlo simulation techniques to find near-optimal transmit and receive filters for a satellite communications link, taking 6 CPU hours on a DECstation 3100. The BER of the link was found to be as much as three orders of magnitude lower when using the MFA-constructed optimal filters than when using filters from other comparison results. For this example, the pulse shapes obtained using MFA exhibit a low BER even as the parameter controlling the nonlinearity of the satellite-link model is varied over a wide range, thus showing the solution is robust.>

A new algorithm, mean field annealing (MFA), is applied to the graph-partitioning problem. The MFA algorithm combines characteristics of the simulated-annealing algorithm and the Hopfield neural network. MFA exhibits the rapid convergence of the neural network while preserving the solution quality afforded by simulated annealing (SA). The rate of convergence of MFA on graph bipartitioning problems is 10-100 times that of SA, with nearly equal quality of solutions. A new modification to mean-field annealing is also presented which supports partitioning graphs into three or more bins, a problem which has previously shown resistance to solution by neural networks. The temperature-behavior of MFA during graph partitioning is analyzed approximately and shown to possess a critical temperature at which most of the optimization occurs. This temperature is analogous to the gain of the neurons in a neural network and can be used to tune such networks for better performance. The value of the repulsion penalty needed to force MFA (or a neural network) to divide a graph into equal-sized pieces is also estimated.