In recent years, task placement technology for reconfigurable FPGA has been developed into 2-D arrays. In this paper, we propose a methodology to pre-place hardware resource into multi-area to achieve the high utilization of hardware resource and reduce used area. The method solves the task type placement problems on the partial dynamic reconfigurable systems. The proposed placement method can provide multi reconfigurable area reusable which depends on each request to load corresponding reconfigurable module into pre-place reconfigurable area. In this experiment, the task placement into the configuration area is using by the tool of Xilinx Plan Ahead 14.1 [15] to analyze and verify on the Xilinx Virtex-6 system development platform. Comparison of related work, the experiment results shown that the proposed placement methodology increases 20.1% the utilization of hardware resources and reduces 61.1% the area of hardware resources.

This paper presents a low complexity digit-serial GF(2m) multiplier. The proposed architecture use digit-serial combination Karatsuba multiplier to reduce area complexity of the circuit. This circuit is suitable for elliptic curve cryptography (ECC) technology. We know that the password system operation core is a multiplier. However that password system multiplier is very big, so it is necessary to reduce the area and time complexity. Therefore, this paper design and implement three smaller multipliers and digit-serial in FPGA to reduce time and area complexity. This method uses 3dm/2 ANDs, (6m+n+3dm/2+m/2+d-7) XORs and (3m-3) registers. Take GF(2340) example, the proposed method compares with related works [12] and [14] which can reduce 70.7% and 50.79% on area, respectively and reduce 50.9% and 73.5% on time, respectively.

As the VLSI technology node advances into the nanometer era, reducing the yield loss induced by via failures is one of the critical problems in design for manufacturability (DFM). Double-via insertion (DVI) in the post-routing stage is a highly recommended method by foundries for improving yield and reliability. This work applies the DVI method in the post stage of an X-architecture clock routing to improve via yield. The proposed DVI-X algorithm constructs the bipartite graphs of the partitioned clock routing layout with single vias and redundant-via candidates (RVCs). Then, a set of maximum cliques is obtained from the bipartite graph for solving the DVI problem. Experimental results on benchmarks indicate that DVI-X can achieve higher double-via insertion rate by 2.925% than other works.

The paper presents a current-mode CMOS image sensor embedded smooth spatial filter algorithm. The sensor includes a 66/spl times/66 pixel array with an on-chip 6-bit analog-to-digital converter that can identify the output value of pixels in gray level resolution. The last row of pixel cells (1/spl times/66) based on the double sampling is used for reducing fixed pattern noise (FPN). Processing circuits are dedicated for the spatial filter algorithm and support reusability to increase the image processing speed and to reduce the design complexity and chip area. The sensor chip has been designed and implemented in TSMC 0.35/spl mu/m 2P4M CMOS mixed-mode process. Each pixel occupies a area of 15.8/spl mu/m/spl times/10.6/spl mu/m with a fill factor of 37.2%. The power consumption is 35.15mW when the sensor operates at 175 frames/second.

The paper first analyzes the crosstalk interaction for two RLC-based clock routings with considering both coupling capacitance and mutual inductance. Running results based on 0.13/spl mu/m process show our observations: (a) the difference between clock delays in different frequencies is very small because the damped factor is always larger than 1 for a long-wire clock routing; (b) the crosstalk interaction can be ignored when two parallel segments are far away over than 23/spl mu/m because the difference between segment delays in a unit length is always less than 3%; (c) the clock delay and skew of two-clock routing with considering crosstalk interaction increase up to 19.1% and 108.8%, respectively. Then, we propose a coupling aware algorithm to generate two-clock routing with considering crosstalk minimization simultaneously. Experimental results show that the clock delay and skew can be improved up to 4.4% and 20%, respectively, than that of no any crosstalk minimization.

Abstract Advancements in hardware and software technologies have made possible the design of real‐time systems and applications where stringent timing constraints are imposed on critical tasks. The design of such systems is more complex than that of temporally unrestricted systems because system correctness depends on the satisfaction of functional as well as temporal requirements. To aid users in correctly and efficiently designing systems, object‐oriented frameworks provide a useful environment for significant reuse and reduction in design effort. In contrast to other application domains, there has been relatively little work on an application framework for the design of real‐time systems. Facing the growing need for real‐time applications, we propose a novel application framework called SESAG, which consists of five components, namely Specifier, Extractor, Scheduler, Allocator, and Generator. Within SESAG, several design patterns are proposed and used for the development of real‐time applications. A new evaluation metric called relative design effort is proposed for evaluating SESAG. Experiences in using SESAG show a significant increase in design productivity through design reuse and a significant decrease in design time and effort. Two complex application examples have been developed using SESAG and evaluated using the new evaluation metric. The examples demonstrate relative design efforts of at most 18% of the design efforts required by conventional methods. Copyright © 2005 John Wiley & Sons, Ltd.

The growing complexity of embedded real-time software requirements calls for the design of reusable software components, the synthesis and generation of software code, and the automatic guarantee of nonfunctional properties such as performance, time constraints, reliability, and security. Available application frameworks targeted at the automatic design of embedded real-time software are poor in integrating functional and nonfunctional requirements. To bridge this gap, we reveal the design flow and the internal architecture of a newly proposed framework called verifiable embedded real-time application framework (VERTAF), which integrates software component-based reuse, formal synthesis, and formal verification. A formal UML-based embedded real-time object model is proposed for component reuse. Formal synthesis employs quasistatic and quasidynamic scheduling with automatic generation of multilayer portable efficient code. Formal verification integrates a model checker kernel from SGM, by adapting it for embedded software. The proposed architecture for VERTAF is component-based and allows plug-and-play for the scheduler and the verifier. Using VERTAF to develop application examples significantly reduced design effort and illustrated how high-level reuse of software components combined with automatic synthesis and verification can increase design productivity.

The rapid escalation in complexity of real-time embedded systems design has made embedded software an integral system part such that formal software synthesis has become an indispensable design automation technique. The current work takes one more step forward in this research direction by proposing a formal synthesis method for complex real-time embedded software. Compared to previous work, our method not only synthesizes embedded software with complex interrelated branching choices for execution within a user-given memory bound, but also tries to guarantee the satisfaction of all user-given local and global time constraints. Our proposed method called time-extended quasi-static scheduling (TEQSS) synthesizes real-time embedded software code from a set of time complex-choice Petri nets. The two most important issues in real-time embedded software, namely memory and time constraints are both elegantly and efficiently handled by TEQSS. We show the feasibility of our method through a master-slave role switch application which is a part of the Bluetooth wireless communication protocol.

Hierarchical hypercubes, such as extended hypercube (EH), hyperweave (HW), and extended hypercube with cross connections (EHC), have been proposed to overcome the scalability limitation of conventional hypercubes through the use of fixed dimension hypercubes of processing elements (PEs) as basic modules interconnected by network controllers (NC) which are themselves interconnected into hypercubes. The scalability of all these three hierarchical hypercube networks is still limited, because the average network communication load in each NC increases as the number of interconnected PEs become very large. In this work a generalization scheme is proposed for improving network scalability, namely transformer cube network (TCN). For illustration purposes, generalized TCN is presented only for EH, though the same scheme can be applied to HW and EHC as well. Several characteristics of TCN, such as topological properties, message routing complexity, fault tolerance, and scalability are analyzed We present a communication algorithm for one-to-one message passing in a fault-free case. Further, the application of TCN to a class of divide-and-conquer problems is shown to have a time complexity of O(log/sub 2/ N), where N is the total number of PEs.

Producing correct software is a major goal for application frameworks that are targeted at embedded real-time systems because incorrect software is of no use and may also cause severe system damage. It is shown how formal verification can be elegantly, seamlessly, and scalably integrated into a component-based object-oriented application framework for embedded real-time systems. Two issues in such technology integration are addressed: (1) the choice of a common system model, and (2) the integration of formal synthesis and model checking. Solutions are provided, respectively, in the form of (1) proposing a new formal object-oriented model (FOOM), and (2) the execution of model checkers within synthesis algorithms. Technically, we propose a compositional software verification framework, in which model checking is employed, with state-space reduction techniques adapted for embedded real-time software. A separate verifier component is proposed for modular integration as illustrated by its implementation in the VERTAF application framework. An example illustrates the success of our approach and the benefits gained through integrating formal verification.

The design of multiprocessor architectures differs from uniprocessor systems in that the number of processors and their interconnection must be considered. This leads to an enormous increase in the design-space exploration time, which is exponential in the total number of system components. The methodology proposed here, called Intelligent Concurrent Object-Oriented Synthesis (ICOS) methodology, makes feasible the synthesis of complex multiprocessor systems through the application of several techiques that speed up the design process. ICOS is based on Performance Synthesis Methodology (PSM), a recently proposed object-oriented system-level design methodology. Four major techniques: object-oriented design, fuzzy design-space exploration, concurrent design, and intelligent reuse of complete subsystems are integrated in ICOS. First, object-oriented modeling and design, through the use of object-oriented relationships and operators, make the whole design process manageable and maintainable in ICOS. Second, fuzzy comparison applied to the specializations or instances of components reduces the exponential growth of design-space exploration in ICOS. Third, independent components from different design alternatives are synthesized in parallel; this design concurrency shortens the overall design time. Lastly, the resynthesis of complete subsystems can be avoided through the application of learning, thus making the methodology intelligent enough to reuse previous design configurations. Experiments show that all these applied techniques contribute to the synthesis efficiency and the degree of automation in ICOS.