Demo Data from VLDB 2026 / reviewers in the wild / expert
Abdelaziz Mzoughi
dblp:33/4031
· DBLP profile ↗
10ranked-venue papers
0as first author
0since 2021 · last 2015
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 7Computer networks · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Storage systems · 46% Memory systems · 19% High-performance computing · 14% | |
| Databases, data mining, and information retrieval
1 paper |
Distributed and cloud data management · 100% |
Topics — the 8 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Distributed and cloud data management › large-scale data management
grid data management |
0.1 | 1 | 2006 | Toward a New Direction on Data Management in Grids · HPDC 2006 |
Storage systems › storage performance
storage device performance |
0.1 | 1 | 2006 | Toward a New Direction on Data Management in Grids · HPDC 2006 |
Parallel and multicore computing › multiprocessor system
shared-memory multiprocessor |
0.0 | 2 | 1992 | The Design of the M3S: A Multiported Shared-Memory Multiprocessor · SC 1992 Towards a Shared-Memory Massively Parallel Multiprocessor · ISCA 1992 |
Memory systems
cache coherence |
0.0 | 1 | 1992 | The Design of the M3S: A Multiported Shared-Memory Multiprocessor · SC 1992 |
Memory systems › cache coherence
directory-based coherence |
0.0 | 1 | 1992 | The Design of the M3S: A Multiported Shared-Memory Multiprocessor · SC 1992 |
Interconnection networks and networks-on-chip › multiprocessor interconnection
processor-memory interconnection |
0.0 | 1 | 1992 | Towards a Shared-Memory Massively Parallel Multiprocessor · ISCA 1992 |
Memory systems › memory architecture
multi-ported memory |
0.0 | 2 | 1992 | The Design of the M3S: A Multiported Shared-Memory Multiprocessor · SC 1992 Towards a Shared-Memory Massively Parallel Multiprocessor · ISCA 1992 |
Memory systems › memory architecture
memory module organization |
0.0 | 1 | 1992 | The Design of the M3S: A Multiported Shared-Memory Multiprocessor · SC 1992 |
Methods — techniques the papers use, named apart from their topics
performance analysis · 0.1simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2015 | Majority Quorum Protocol Dedicated to General Threshold SchemesabstractIn this paper, we introduce a majority quorum system dedicated to p-m-n general threshold schemes where p, n and m are respectively the minimal number of chunks that provide some information (but not necessarily all) on the original data, the total number of nodes in which the chunks of an object are stored and the minimal number of nodes needed to retrieve the original data using this protocol. In other words, less than p chunks reveal absolutely no information about the original data and less than m chunks can't reconstruct the original data. The p-m-n general threshold schemes optimize the usage of storage resources by reducing the total size of data to write and ensure fault-tolerance up to (n -- m) nodes failure. With such a data distribution, a specific value of m can be set to have a good trade off between resources utilization and fault-tolerance. The only drawback of such schemes is the lack of any consistency protocol. If fact, consistency protocols like classical majority quorum are based on full replication. To successfully read or write a data using the majority quorum protocol, an absolute majority of replicas must be read / written correctly. This condition ensures that any read and write operations will contain at least one common replica, which guarantees their consistency. However, when a threshold scheme is used, an adaptation is needed. In fact, classical majority quorum protocol can no longer ensure that m chunks will have the latest version when [n/2] + 1 Théodore Jean Richard Relaza, Jacques Jorda, Abdelaziz Mzoughi |
CCGRID | 3 |
| 2009 | VisageFS Translucent Directories: Efficient Posix Consistencies for Wide-Area WorkflowsabstractOne of the key challenges related to the grid environment is to efficiently use the storage resources of compute nodes. Therefore, we have developed the ViSaGe solution which features VisageFS - a POSIX-compliant wide-area file system, VCCC - a distributed lock mechanism, and VRT - a storage virtualization layer. In this paper, we present the VisageFStranslucentdirectoryproperty which enables a dynamic, transparent and efficient use of local storage by means of hierarchical Posix consistencies. Nodes that access a translucent enabled shared-directory will see different contents according to the site or node-level POSIX consistency. Thereafter, one of the various reconciliation modes re-enables the grid-level POSIX consistency. Our "nevermind'' mode does it inconstanttime. François Thiébolt, Aurélien Ortiz, Abdelaziz Mzoughi |
PDP | 3 |
| 2008 | Mobility prediction based on an ant system
Mehammed Daoui, Abdelaziz Mzoughi, Mustapha Lalam, Malika Belkadi, Rachida Aoudjit |
Comput. Commun. | 2 |
| 2006 | Toward a New Direction on Data Management in GridsabstractA great number of scientific applications that access to a large amount of data have emerged last few years. For example in high energy physics, the volume of data will be measured in petabytes in the next years. Grids seek to aggregate geographically distributed resources for the need of these applications. It results that scientists have to deal with many problems to manage available data over the grid. Since grid resources are interconnected by WAN, the main speculation is that data transfers over the grid are bounded by network latency and bandwidth. Here, we point out some storage device issues which in many cases invalidate this assumption. Implicitly, we give a new direction that will lead to a better utilization of available resources on a grid Aurélien Ortiz, Jacques Jorda, Abdelaziz Mzoughi |
HPDC | 3 |
| 2006 | How to Achieve High Throughput with Dynamic Tree-Structured CoterieabstractData replication permits a better network bandwidth utilization and minimizes the effect of latency in large-scale systems such as computing grids. However, the cost of maintaining the data consistent between replicas may become difficult if the read/write system has to ensure sequential consistency. In this paper, we limit the overhead due to the data consistency protocols by introducing a new dynamic quorum protocol called the elementary permutation protocol. This protocol permits the dynamic reconfiguration of a tree-structured coterie (Agrawal and Abbadi, 1991) in function of the load of the machines that possess the data replicas. It applies a tree transformation in order to obtain a new less loaded coterie. This permutation is based on the load information of a small group of machines possessing the copies. The implementation and the evaluation of our algorithm have been based on the existing atomic read/write service of Lynch and Shvartsman (1997). We demonstrate that the elementary permutation ameliorates the system's throughput up to 50% in the best case. The results of our simulation show that the tree reconfiguration based on the elementary permutation is more efficient for a relatively small number of copies Ivan Frain, Abdelaziz Mzoughi, Jean Paul Bahsoun |
ISPDC | 2 |
| 1996 | Performance of the Vectorial Processor VEC-SM2 Using Serial Multiport MemoryabstractComplex scientific problems involving large volumes of data need a huge computing power.Memory bandwidth remains a key issue in high performance systems.This paper presents an originrd method of memory organization, based on serial multiport memory components, which allows simultaneous access to all ports without causing either cortfhct between them or suspension.The resulting process for information exchange gives a cost-effective realization of a data memory for vector processors.The memory bandwidth can be increased considerably in a modular manner, without practical implementation constraints.The information exchange on the serial links guarantees a continuous data flow and the reaching of a maximum yield of the pipeline, thus avoiding the step-by-step feeding of the pipeline operator. Jacques Jorda, Abdelaziz Mzoughi, O. Lafontaine, Daniel Litaize |
International Conference on Supercomputing | 2 |
| 1995 | Multiple-Base Storage Scheme Theory-Applications to 2D and 3D Parallel Arrays
Jacques Jorda, Abdelaziz Mzoughi, Daniel Litaize |
ICPP (1) | 2 |
| 1995 | Semi-linear and Bi-base Storage Schemes Classes: General Overview and Case Study
Jacques Jorda, Abdelaziz Mzoughi, Daniel Litaize |
International Conference on Supercomputing | 2 |
| 1992 | Towards a Shared-Memory Massively Parallel MultiprocessorabstractA set of ultra high throughput (more than one Gigabits per second) serial links used as processor-memory network can lead to the starting up of a shared-memory massively parallel multiprocessor. The bandwidth of the network is far beyond values found in present shared-memory multiprocessor networks. To feed this network the memory must be serially multiported. Such a multiprocessor can actually be build with current technologies. Daniel Litaize, Abdelaziz Mzoughi, Christine Rochange, Pascal Sainrat |
ISCA | 2 |
| 1992 | The Design of the M3S: A Multiported Shared-Memory MultiprocessorabstractThe design of M3S, an academic shared-memory multiprocessor, is described. The memory is divided into modules. Each processor (through its cache) has an access to each memory module only through a high-throughput private serial link. Each memory module has several serial ports that are connected, in parallel, to the memory. The data coherency is maintained by a hardware directory-based scheme. The interconnection network has no bottleneck since each processor has its private path to each memory module. The high bit rate of the serial links is the most important technical problem for the design of this prototype. Synchronous solutions have been chosen in the prototype because of their greater simplicity. The data rate on the serial links is 800 Mb/s. Choices made in order to realize this project with one memory module and sixteen processor modules are explained.> Pascal Sainrat, Abdelaziz Mzoughi, Christine Rochange, Daniel Litaize |
SC | 2 |