Pipelined computation of very large word-length LNS addition/subtraction requires a significant amount of hardware and long pipeline latency. We propose a base-e exponential algorithm to simplify the exponential computation and to replace half of the pipeline stages by multiplication-and-accumulate operations. By using this approach, the circuit cost of the previously proposed 64 bit pipelined LNS addition/subtraction unit can be reduced by more than fifty percent. We also developed signed-digit (SD) algorithms to further enhance the performance of the LNS computation. From our analysis, the throughput of the 64 bit LNS unit can be increased by a factor of 4.62, and the pipeline latency can be reduced by a factor of seven. Furthermore, this SD approach can still save more than 50% of the table size and 27.6% of the circuit of the previously proposed LNS unit. The proposed approaches and algorithms have been verified by comprehensive simulations on the designed 32 bit SD hardware-reduced LNS unit. We have concluded that the proposed approaches can significantly improve the performance of very large word-length LNS addition/subtraction computation.

Conventional additive normalization methods suffer from its linear convergence rate. We propose a new additive normalization method for the computation of exponential function. This new method can allow the values of the normalization factors be obtained directly from the remaining terms without any computation. Furthermore, the number of the normalization factors that are obtained in each normalization stage is twice that obtained from its previous stage. As a result, the convergence rate of our method is exponential. These two advantages of our new method can significantly enhance the speed and reduce the hardware cost of the additive normalization method. Based on our proposed additive normalization method, we have designed the architectures of a 24-bit exponential unit and a 53-bit exponential unit. From the results of our thorough simulations on the 24-bit unit, we have verified that our proposed algorithm and our error analysis method are correct.

A novel pipelined method is proposed to compute the addition/subtraction in very large word-length logarithmic number system (LNS) arithmetic. Digit-parallel additive-normalization and digit on-line multiplicative-normalization methods are adopted to compute the exponential and logarithmic functions, respectively, in LNS addition/subtraction. These two methods can both be implemented in a pipelined and regular architecture. The size of the required lookup tables is now proportional to a third-order polynomial function, instead of an exponential function, of the word length. The total size of the tables in a 32-bit LNS unit is estimated to be less than 53.5 kbits and the total size of the table's in a 64-bit LNS unit will be less than 471 kbits. Furthermore, the hardware cost of the other circuits in the proposed LNS unit is only proportional to the square of the word length. This study also develops a simple leading-zero-bits prediction technique that can significantly enhance the precision in LNS addition/subtraction computation. When compared to floating-point arithmetic design, our approach still suffers from large hardware cost and pipeline latency. However, the proposed approach has provided a theoretical advancement in the development of very large word-length LNS arithmetic.