Demo Data from VLDB 2026 / reviewers in the wild / expert
Akio Shimada
dblp:33/5654
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 2014
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 77% Processor architecture and microarchitecture · 23% | |
| Software engineering, system software, and programming languages
1 paper |
Operating systems · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Operating systems › resource management
memory management |
0.2 | 1 | 2014 | CMCP: a novel page replacement policy for system level hierarchical memory management on many-cores · HPDC 2014 |
Memory systems › memory hierarchy
memory hierarchy management |
0.2 | 1 | 2014 | CMCP: a novel page replacement policy for system level hierarchical memory management on many-cores · HPDC 2014 |
Memory systems › memory management › virtual memory
page replacement |
0.2 | 1 | 2014 | CMCP: a novel page replacement policy for system level hierarchical memory management on many-cores · HPDC 2014 |
Processor architecture and microarchitecture › special-purpose processor
coprocessor |
0.1 | 1 | 2014 | CMCP: a novel page replacement policy for system level hierarchical memory management on many-cores · HPDC 2014 |
Processor architecture and microarchitecture › many-core architecture
intel xeon phi |
0.1 | 1 | 2014 | CMCP: a novel page replacement policy for system level hierarchical memory management on many-cores · HPDC 2014 |
Methods — techniques the papers use, named apart from their topics
OS-level memory management · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2014 | CMCP: a novel page replacement policy for system level hierarchical memory management on many-coresabstractThe increasing prevalence of co-processors such as the Intel Xeon Phi, has been reshaping the high performance computing (HPC) landscape. The Xeon Phi comes with a large number of power efficient CPU cores, but at the same time, it's a highly memory constraint environment leaving the task of memory management entirely up to application developers. To reduce programming complexity, we are focusing on application transparent, operating system (OS) level hierarchical memory management. Balazs Gerofi, Akio Shimada, Atsushi Hori, Masamichi Takagi, Yutaka Ishikawa |
HPDC | 2 |
| 2013 | Partially Separated Page Tables for Efficient Operating System Assisted Hierarchical Memory Management on Heterogeneous ArchitecturesabstractHeterogeneous architectures, where a multicore processor is accompanied with a large number of simpler, but more power-efficient CPU cores optimized for parallel workloads, are receiving a lot of attention recently. At present, these co-processors, such as the Intel Xeon Phi product family, come with limited on-board memory, which requires partitioning computational problems manually into pieces that can fit into the device's RAM, as well as efficiently overlapping computation and communication. In this paper we propose an application transparent, operating system (OS)assisted hierarchical memory management system, where the OS orchestrates data movement between the host and the device and updates the process virtual memory address space accordingly. We identify the main scalability issues of frequent address space changes, such as the increasing price of TLB invalidations with the growing number of CPU cores, and propose partially separated page tables with address-range CPU masks to overcome the problem. With partially separated page tables each core maintains its own set of mappings of the computation area, enabling the OS to perform address space updates in a scalable manner, and involve a particular CPU core in TLB invalidation only if it is absolutely necessary. Furthermore, we propose dedicated data movement cores in order to efficiently overlap computation and communication. We provide experimental results on stencil computation, a common HPCkernel, and show that OS assisted memory management has the potential for scalable transparent data movement. Balazs Gerofi, Akio Shimada, Atsushi Hori, Yutaka Ishikawa |
CCGRID | 2 |
| 2007 | Finding candidate spots for replica servers based on demand fluctuationabstractMany service providers distribute various kinds of content over the Internet. They often use replica servers to provide stable service. To position them appropriately, service providers must predict the demands for their services and provide computing capacity sufficient for servicing the demands. Unfortunately, predicting demands is difficult because demand for a service usually fluctuates. Our research group is developing ExaPeer, an infrastructure that apportions computing capacity to services running on hundreds or thousands of trusted machines all over the Internet. In this paper, we describe ExaPeer’s approach to dynamically selecting candidate spots for replica servers. The runtime system in ExaPeer detects fluctuations in demand and then dynamically selects candidate spots on which replica servers should be placed to best meet the demand. Experimental results demonstrate that the candidate spots selected by ExaPeer work better than manually selected ones even if the scale of demand changes rapidly. Masato Asahara, Akio Shimada, Kenji Kono |
ICPADS | 2 |