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M. Rajagopalan

dblp:33/6702 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 100%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization › instruction scheduling
software pipelining		 0.011993
Efficient scheduling of fine grain parallelism in loops · MICRO 1993
Processor architecture and microarchitecture › instruction-level parallelism
VLIW		 0.011993
Efficient scheduling of fine grain parallelism in loops · MICRO 1993
Processor architecture and microarchitecture › register file
register file design		 0.011993
Efficient scheduling of fine grain parallelism in loops · MICRO 1993

Methods — techniques the papers use, named apart from their topics

shifting register files · 0.0modulo variable expansion · 0.0
YearPublicationVenuePosition
1993 Efficient scheduling of fine grain parallelism in loops
abstract
Anti-dependencies are a major cause of bottleneck in software pipelining. Anti-dependencies can be removed in software by code duplication as in the technique of modulo variable expansion. However, it is possible to eliminate anti-dependencies in hardware. So far, two such VLIW architectures have been proposed: polycyclic and URPR-1 architectures. These architectures also introduce attractive solutions for the memory contention problem in general. We, on the other hand, propose a more cost-effective architecture for the same purpose: SRFA. SRFA is based on "shifting register files".>
M. Rajagopalan, Vicki H. Allan
 MICRO1