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Mondira (Mandy) Deb Pant

dblp:33/8364 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2013
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Energy-efficient computing · 50% Integrated circuit design · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Energy-efficient computing
power management
0.212013
Power management and delivery for high-performance microprocessors · DAC 2013
Integrated circuit design › power delivery network
voltage regulator
0.212013
Power management and delivery for high-performance microprocessors · DAC 2013
YearPublicationVenuePosition
2013 Power management and delivery for high-performance microprocessors
abstract
This paper provides an introduction to advanced power management and delivery techniques that have been employed in leading microprocessor designs. The techniques need multiple voltage rails supplied by independent voltage regulators. We provide justification for near-load regulators and explain the practical challenges associated with the regulator integration.
Tanay Karnik, Mondira (Mandy) Deb Pant, Shekhar Borkar
DAC2
2010 Microprocessor power delivery challenges in the Nano-Era
abstract
A robust power grid is pivotal in meeting performance targets and guaranteeing reliable operation of high-performance microprocessors. Higher device densities and faster switching frequencies cause large switching currents through flow through the power and ground networks which degrade performance and reliability. Excessive resulting voltage drops in the power grid reduce switching speeds and decrease noise margins of the circuits and inject noise which may lead to functional failures. Further, high average current densities lead to undesirable wearing out of metal wires due to electro-migration. Achieving and maintaining excellent voltage regulation at the consumption points notwithstanding the wide fluctuations in the power demands across the chip is definitely the key to avoiding an unruly power grid. During this tutorial, I plan on talking about not only the fundamentals of on-die power delivery but also discusses chief challenges involved in designing a robust and reliable power grid including verification against design targets using in-house/vendor tools in the nano-era.
Mondira (Mandy) Deb Pant
ISLPED1