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Syed K. Islam

dblp:33/9350 · also Syed Kamrul Islam · DBLP profile ↗
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8ranked-venue papers
0as first author
4since 2021 · last 2025
0000-0002-0501-0027ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 5 · 4 since 2021Systems, architecture and hardware · 3Human-computer interaction and ubiquitous computing · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Artificial intelligence
1 paper
Efficient and distributed learning · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 100%
Computer networks
1 paper
Edge and fog computing · 100%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Machine learning › Efficient and distributed learning
model compression
0.712023
Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review · Proc. IEEE 2023
Hardware accelerators and domain-specific architectures › machine learning accelerator › DNN inference accelerator
edge inference accelerator
0.712023
Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review · Proc. IEEE 2023
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.712023
Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review · Proc. IEEE 2023
Edge and fog computing
edge inference
0.212023
Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review · Proc. IEEE 2023

Methods — techniques the papers use, named apart from their topics

quantization · 2.0pruning · 2.0DNN architecture design · 2.0
YearPublicationVenuePosition
2025 Enhancing Student Self-Efficacy and Interest in Microelectronics Through Immersive Virtual Reality in an Informal Learning Environment
abstract
This study investigates iVRLab, an immersive virtual reality (VR) microfabrication training system, and its influence on college students' self-efficacy and interest in microelectronics during a one-hour workshop held within a 1.5-day training camp. iVRLab simulates photolithography cleanroom operations, providing hands-on virtual experiences that merge theory with practice. A pre-post analysis revealed a significant rise in self-efficacy (M = 4.11 to 4.37, p = 0.0066), demonstrating the system's effectiveness in building confidence. Although interest only showed slight gains, high baseline scores (3.6-3.7 on a 4-point scale) indicate a ceiling effect. Correlations among engagement, embodiment (r = 0.91, p < 0.001), and immersion (r = 0.60, p < 0.01) underscore the value of active, embodied VR learning. Qualitative feedback further highlighted iVRLab's immersive realism and its capacity to spark curiosity about microfabrication careers. These findings suggest that VR training can effectively boost self-efficacy in microelectronics, reinforcing students' enthusiasm in an informal learning setting and indicating the potential broader adoption across STEM fields.
Yupei Duan, Fang Wang 0024, Chi-Ren Shyu, Syed K. Islam, Sazia A. Eliza, Jim Flink, Hao He 0009, Shangman Li, Scottie Murrell, Amith Nalmas
ICALT5
2025 Students' Motivation in STEM Education through a Microelectronics Training Program: Through the Lens of the ARCS Model of Motivational Design
abstract
In this study, we examined the effects of a 1.5-day microelectronics training program on students' self-efficacy. Using a quasi-experimental design (N = 27), we analyzed the data through a paired t-test complemented by qualitative insights. The findings revealed that: (1) a short-term microelectronics training program, designed based on the Attention, Relevance, Confidence, and Satisfaction (ARCS) motivational model, can positively influence learners' self-efficacy toward STEM education; and (2) incorporating diverse instructional strategies-such as guest talks from industry and academic experts, along with hands-on, real-world experiences-is essential for making abstract textbook concepts more concrete and inspiring students to pursue STEM-related careers.
Chi-Ren Shyu, Syed K. Islam, Sazia A. Eliza, Jim Flink
ICALT4
2023 Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review
abstract
Successful integration of deep neural networks (DNNs) or deep learning (DL) has resulted in breakthroughs in many areas. However, deploying these highly accurate models for data-driven, learned, automatic, and practical machine learning (ML) solutions to end-user applications remains challenging. DL algorithms are often computationally expensive, power-hungry, and require large memory to process complex and iterative operations of millions of parameters. Hence, training and inference of DL models are typically performed on high-performance computing (HPC) clusters in the cloud. Data transmission to the cloud results in high latency, round-trip delay, security and privacy concerns, and the inability of real-time decisions. Thus, processing on edge devices can significantly reduce cloud transmission cost. Edge devices are end devices closest to the user, such as mobile phones, cyber–physical systems (CPSs), wearables, the Internet of Things (IoT), embedded and autonomous systems, and intelligent sensors. These devices have limited memory, computing resources, and power-handling capability. Therefore, optimization techniques at both the hardware and software levels have been developed to handle the DL deployment efficiently on the edge. Understanding the existing research, challenges, and opportunities is fundamental to leveraging the next generation of edge devices with artificial intelligence (AI) capability. Mainly, four research directions have been pursued for efficient DL inference on edge devices: 1) novel DL architecture and algorithm design; 2) optimization of existing DL methods; 3) development of algorithm–hardware codesign; and 4) efficient accelerator design for DL deployment. This article focuses on surveying each of the four research directions, providing a comprehensive review of the state-of-the-art tools and techniques for efficient edge inference.
Md Maruf Hossain Shuvo, Syed K. Islam, Jianlin Cheng, Bashir I. Morshed
Proc. IEEE2
2023 Deep Multitask Learning by Stacked Long Short-Term Memory for Predicting Personalized Blood Glucose Concentration
abstract
The adverse glycemic events triggered by the inaccurate insulin infusion in Type I diabetes (T1D) can lead to fatal complications. Predicting blood glucose concentration (BGC) based on clinical health records is critical for control algorithms in the artificial pancreas (AP) and aiding in medical decision support. This paper presents a novel deep learning (DL) model incorporating multitask learning (MTL) for personalized blood glucose prediction. The network architecture consists of shared and clustered hidden layers. Two layers of stacked long short-term memory (LSTM) form the shared hidden layers that learn generalized features from all subjects. The clustered hidden layers comprise two dense layers adapting to the gender-specific variability in the data. Finally, the subject-specific dense layers offer additional fine-tuning to personalized glucose dynamics resulting in an accurate BGC prediction at the output. OhioT1DM clinical dataset is used for the training and performance evaluation of the proposed model. A detailed analytical and clinical assessment have been performed using root mean square (RMSE), mean absolute error (MAE), and Clarke error grid analysis (EGA), respectively, which demonstrates the robustness and reliability of the proposed method. Consistently leading performance has been achieved for 30- (RMSE = 16.06 $\pm$ 2.74, MAE = 10.64 $\pm$ 1.35), 60- (RMSE = 30.89 $\pm$ 4.31, MAE = 22.07 $\pm$ 2.96), 90- (RMSE = 40.51 $\pm$ 5.16, MAE = 30.16 $\pm$ 4.10), and 120-minute (RMSE = 47.39 $\pm$ 5.62, MAE = 36.36 $\pm$ 4.54) prediction horizon (PH). In addition, the EGA analysis confirms the clinical feasibility by maintaining more than 94% BGC predictions in the clinically safe zone for up to 120-minute PH. Moreover, the improvement is established by benchmarking against the state-of-the-art statistical, machine learning (ML), and deep learning (DL) methods.
Md Maruf Hossain Shuvo, Syed K. Islam
IEEE J. Biomed. Health Informatics2
2018 Inkjet printed thin film electronic traces on paper for low-cost body-worn electronic patch sensors
abstract
Patch sensors are slowly becoming ubiquitous in the market for wearable devices. They can collect and send data unobtrusively, which is beneficial to several applications in healthcare, sports, and fitness industries. Patch sensor by inkjet printing (IJP) with functional materials on flexible substrates allows design flexibility and portability at a very low cost. In this paper, preliminary results on characterization of IJP resistors printed with a variety of inks on substrates such as paper and polyimide have been reported, followed by a discussion on printed breath-rate and ECG sensors. The results promise a plethora of possibilities in printed circuits.
Ankita Mohapatra, Bashir I. Morshed, Samira Shamsir, Syed K. Islam
BSN4
2017 A novel charge sensitive pre-amplifier structure for biological temperature readout applications
abstract
Charge sensitive pre-amplifier architectures have been studied for decades for various applications, most of which adopt a gain stage with capacitor feedback to integrate the signal and a reset path to provide DC bias. For the biological temperature readout front-end, we propose a novel structure without the gain stage, which implies a strong potential for fully integrated high frequency applications. The proposed design provides 0.94 mV/pC gain with high conversion linearity while consuming only 1.4 micro watts of power with buffer under a 1.2-V supply rail. The prototype occupying a chip area of 0.038 square millimeter is fabricated in 130 nm standard CMOS process.
Hanfeng Wang, Song Yuan, Syed K. Islam, Charles L. Britton Jr.
ISCAS3
2016 In tegration of carbon nanostructures on CMOS for lab-on-a-chip sensing
abstract
We review the challenges and suggest future directions of carbon nanostructure CMOS integration for lab-on-a-chip systems. Power and area requirements of standard benchtop sensor instrumentation limits their use in portable applications. We have been developing carbon based nanostructures and low power analog readouts to enable sensitive and highly efficient sensor measurement in a single measurement platform. Specifically, we review integration methods for carbon nanofibers and nanospikes with sensor readouts on a CMOS platform. These lab-on-chip systems offer high throughput, require low operating power and allow complete system implementation in portable and implantable devices.
Khandaker A. Al Mamun, Jinlong Gu, Dale K. Hensley, Syed K. Islam, Nicole McFarlane
ISCAS4
2008 Genetically-engineered whole-cell bioreporters on integrated circuits for environmental monitoring
abstract
A bioluminescent bioreporter integrated circuit (BBIC) biosensor for environmental monitoring is presented. The bioluminescent bioreporters are bacteria that can be genetically altered to achieve bioluminescence when in contact with a targeted substance. The bioreporters are placed on a microluminometer. The microluminometer includes integrated photodiodes and signal processing circuits and is realized in a standard CMOS process. The BBIC can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescene 5RL bacteria and provides a integrated biosensor platform for environmental and food/water safety monitoring.
Nora D. Bull, Syed K. Islam, Benjamin J. Blalock, Steven Ripp, Scott Moser, Gary S. Sayler
ISCAS2