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Fardin Derogarian

dblp:33/9782 · DBLP profile ↗
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3ranked-venue papers
3as first author
0since 2021 · last 2020
0000-0001-6141-1637ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-authorComputer networks · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 50% Embedded and real-time systems · 50%
Computer networks
1 paper
Internet of things and sensor networks · 100%

Topics — the 3 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › analog and mixed-signal circuits
mixed-signal circuit design
0.412020
A Multifunctional Integrated Circuit Router for Body Area Network Wearable Systems · IEEE/ACM Trans. Netw. 2020
Internet of things and sensor networks › iot networks › iot connectivity
mesh topology
0.112020
A Multifunctional Integrated Circuit Router for Body Area Network Wearable Systems · IEEE/ACM Trans. Netw. 2020
Internet of things and sensor networks
wireless body area network
0.112020
A Multifunctional Integrated Circuit Router for Body Area Network Wearable Systems · IEEE/ACM Trans. Netw. 2020

Methods — techniques the papers use, named apart from their topics

time synchronization protocol · 0.9CMOS · 0.9
YearPublicationVenuePosition
2020 A Multifunctional Integrated Circuit Router for Body Area Network Wearable Systems
abstract
A multifunctional router IC to be included in the nodes of a wearable body sensor network is described and evaluated. The router targets different application scenarios, especially those including tens of sensors, embedded into textile materials and with high data-rate communication demands. The router IC supports two different functionality sets, one for sensor nodes and another for the base node, both based on the same circuit module. The nodes are connected to each other by means of woven thick conductive yarns forming a mesh topology with the base node at the center. From the standpoint of the network, each sensor node is a four port router capable of handling packets from destination nodes to the base node, with sufficient redundant paths. The adopted hybrid circuit and packet switching scheme significantly improve network performance in terms of end-to-end delay, throughput and power consumption. The IC also implements a highly precise, sub-microsecond one-way time synchronization protocol which is used for time stamping the acquired data. The communication module was implemented in a 4-metal,$0.35~\mu \text{m}$CMOS technology. The maximum data rate of the system is 35 Mbps while supporting up to 250 sensors, which exceeds current BAN applications scenarios.
Fardin Derogarian, João Canas Ferreira, Vítor Grade Tavares, José Machado da Silva, Fernando J. Velez
IEEE/ACM Trans. Netw.1
2014 A Time Synchronization Circuit with an Average 4.6 ns One-Hop Skew for Wired Wearable Networks
abstract
This paper describes and evaluates a fully digital circuit for one-way master-to-slave highly precise time synchronization in a low-power, wearable system equipped with a set of sensor nodes connected in a mesh network. Sensors are connected to each other with conductive yarns that are used as one-wire bidirectional communication links. The circuit is designed to perform synchronization in the Medium Access Control (MAC) layer. In each sensor node, the synchronization circuit provides a synchronized, programmable clock signal and a real-time counter for time stamping. Experimental results obtained with an implementation in 0.35 μm CMOS technology for a network of electromyography sensors show that the circuit keeps the one-hop average clock skew below 4.6 ns, a value small enough to satisfy many wearable application requirements.
Fardin Derogarian, João Canas Ferreira, Vítor Grade Tavares
DSD1
2012 Design and Implementation of a Circuit for Mesh Networks with Application in Body Area Networks
abstract
This paper presents a network circuit for wearable low-power BAN (Body Area Networks) applications, geared towards mesh network topologies with conductive yarns as transmission channels. The design and implementation of the physical and MAC layers is described. The resulting circuit sends and receives data simultaneously, and experimental results indicate that the proposed system works with variable data rates, up to a maximum of 9+9 Mbps. All reported measurements were collected from working FPGA-based prototypes, and the performance achieved shows that the circuit is suitable for use in reliable high-speed low-power BAN applications.
Fardin Derogarian, João Canas Ferreira, Vítor Grade Tavares
DSD1