It is well-known that operating transistors in low-temperature environments improves their characteristics. This has led to the expansion of integrated circuit (IC) applications at low temperatures, including high-performance computers and controllers for quantum computers. On the other hand, hardware Trojans (HTs) pose a severe concern, threatening the authenticity of ICs. This study proposes a new HT circuit, referred to as Cryo-HT, that can be activated by the increased discharge time of a metal-oxide-semiconductor (MOS) capacitor at low temperatures. We fabricated an advanced encryption standard (AES) circuit with Cryo-HT using 180 nm process technology. We demonstrate that Cryo-HT is not activated at room temperature but activates at 213 K to reveal the AES encryption key.

Two types of ring oscillators (ROs) fabricated using a 65 nm FD-SOI process were used to compare total ionizing dose (TID) characteristics under gamma-ray and alpha-ray irradiation. By employing two ROs with nearly identical circuit structures, the electric field dependence of the TID effect was evaluated. Gamma-ray irradiation resulted in significant degradation differences between the ROs, indicating strong electric field dependence, whereas alpha-ray irradiation showed negligible differences, suggesting weak dependence. These variations are attributed to differences in initial recombination rates due to the higher linear energy transfer (LET) of alpha particles than gamma-rays. Additionally, the recovery rate under alpha-ray irradiation was lower than that under gamma-ray irradiation. These findings suggest that when using alpha-ray irradiation as an alternative to gamma-ray irradiation, compensation is mandatory.

In 22 nm FDSOI, the flip-well structure is used instead of the standard-well structure. We evaluated soft-error tolerance by heavy-ion irradiation tests on standard and stacked flip-flops (STDFF and STACKEDFF) in the flip-well structure. The error probability of STACKEDFF was significantly smaller than STDFF. Therefore, the stacked structure is also effective against soft error in the flip-well structure. However, as the supply voltage is lowered, even STACKEDFF becomes vulnerable to soft errors under certain conditions. The origin of these errors was pMOSFETs. Therefore, soft error countermeasures are needed to account for errors from pMOSFETs.

We examined the radiation hardness of the several types of flip-flops fabricated in a 130 nm bulk process by alpha-ray irradiation tests and circuit simulation. The simulated $\alpha -$SER of FFs with the critical charge larger than 14 fC becomes 1/100 of that with the critical charge of 10 fC. We propose a radiation-hardened flip-flop minimizing area, delay, and power overheads with 1/100 lower $\alpha -$SER in a 130 nm bulk process. The radiation hardness is achieved by adding series transistors and wires with only less than 14% area, 7% delay, and 12% power overheads in order to increase the critical charge. Alpha-ray irradiation tests revealed that the proposed method can reduce soft error rates to 1/100.