VLDB 2026 Research / reviewers in the wild / expert
Jiafan Xu
dblp:331/8566
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2023
0009-0007-9063-2480ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization
deep learning compiler |
0.7 | 1 | 2023 | ALT: Breaking the Wall between Data Layout and Loop Optimizations for Deep Learning Compilation · EuroSys 2023 |
Compilers and program optimization
loop optimization |
0.7 | 1 | 2023 | ALT: Breaking the Wall between Data Layout and Loop Optimizations for Deep Learning Compilation · EuroSys 2023 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
DNN accelerator |
0.2 | 1 | 2023 | ALT: Breaking the Wall between Data Layout and Loop Optimizations for Deep Learning Compilation · EuroSys 2023 |
Methods — techniques the papers use, named apart from their topics
equality saturation · 1.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | ALT: Breaking the Wall between Data Layout and Loop Optimizations for Deep Learning CompilationabstractDeep learning models rely on highly optimized tensor libraries for efficient inference on heterogeneous hardware. Current deep compilers typically predetermine layouts of tensors and then optimize loops of operators. However, such unidirectional and one-off workflow strictly separates graph-level optimization and operator-level optimization into different system layers, missing opportunities for unified tuning. Zhiying Xu, Jiafan Xu, Hongding Peng, Wei Wang 0002, Xiaoliang Wang 0001, Haoran Wan, Haipeng Dai 0001, Yixu Xu, Hao Cheng 0004, Kun Wang 0005, Guihai Chen |
EuroSys | 2 |