Extensive compiler support is a key-necessity for the general acceptance and usability of the promising Coarse Grained Reconfigurable Array (CGRA) accelerator architecture. However, there is currently little work to seamlessly connect mathematical graph-based modeling/programming languages and graph-based intermediate representations into a model-based semi-automatic compilation flow in which experts from different domains can collaborate interactively. Therefore, we present a flexible graph language with well-defined execution semantics which facilitates this intended compilation flow by supporting multiple user-defined abstractions. Starting with an abstract mathematical kernel description, we show that different mappings to a modern CGRA can be explored in an under-standable way with our language. We argue that our work is a promising starting point to increase the understandability and accessibility of CGRA compilation.

In an electronic system level design flow, early timing predictions can be realized by employing virtual platform simulations in the transaction level abstraction. However, there is little research comparing virtual platform solutions for small RISC-V based System-on-a-Chip architectures. This paper tries to fill this gap with a qualitative and quantitative comparison focusing on timing prediction accuracy. Starting with a total list of 25 RISC-V simulators, we found that only three candidates fulfill a comprehensive set of requirements for research applications. For these candidates we performed a quantitative comparison in which we model a single-master bus-based System-on-a-Chip at different abstraction levels and measure each simulator’s timing prediction accuracy and simulation speed.