Voltage-controlled oscillator (VCO)-based comparators offer higher energy efficiency as the difference in input magnitudes increase, such as in level-crossing ADCs. Nevertheless, to date, they require a clock signal to perform comparison operations. This is incongruous with continuous-time applications, where inputs are compared continuously. Further, they lack hysteresis, a crucial feature for mitigating spurious switching that compromises energy efficiency. In this paper, we present a novel VCO-based comparator that, for the first time, simultaneously achieves continuous-time operation and high energy efficiency. The former feature is enabled by a novel continuous-time decision circuit, while the latter is achieved through a novel switched-current hysteresis circuit that mitigates spurious switching. The proposed comparator is designed in 65 nm CMOS. Simulation results show that it achieves low energy per comparison, ranging from 0.07 to 4 pJ, with an average propagation delay of ~15 ns. The average energy consumption is 0.19 pJ — ~1.8× lower than the state-of-the-art VCO-based comparator.

This paper presents a novel digital inductor-current estimator for digitally-controlled current-ripple-based synchronous DC-DC buck converters. The estimator features high accuracy, which is imperative for current-ripple control that requires precise estimation of instantaneous DC and inductor ripple currents in both the discontinuous and continuous conduction modes. The estimation method indirectly determines the currents by constructing a digital representation of the voltage across the inductor, rendering it applicable in both conduction modes. This method is more accurate and simpler than conventional methods that estimate DC and inductor ripple currents directly in each conduction mode. Compared to state-of-the-art methods, the proposed estimator achieves an average DC current estimation error that is ≥5.7× smaller and an inductor ripple current estimation error that is ≤ 1.90% over various load conditions.

In battery-powered devices, power-efficient power management systems, such as high-power-efficiency buck-boost converters, are critical. In this paper, we propose a novel digital-input average current mode high-power-efficiency buck-boost converter. The proposed buck-boost converter embodies a novel full-cycle continuous current sensing circuit, which eliminates the need for a current selection circuit by continuously sensing the inductor current throughout the entire switching cycle. Unlike conventional approaches which rely on non-continuous sensing, this method improves current sensing accuracy and eliminates false switching, leading to reduced output noise, increased power efficiency, and improved circuit robustness. The proposed buck-boost converter further embodies a PWM controller with novel adaptive mode control, which dynamically adjusts the pulse width of the power transistors in buck-boost operation - this is to avoid narrow pulses hence preventing false switching. This further enhances the power efficiency and the robustness of the buck-boost converter. Both the proposed full-cycle continuous current sensing circuit and the adaptive mode control circuit are simple, with little hardware or power dissipation overheads. The proposed buck-boost converter is designed and fabricated in a 55nm BCD process with an IC area of 2.4mm2. Based on measurements, the proposed buck-boost converter features a high peak power efficiency of 95% and maintains a high efficiency of >90% across a wide output range (0.3W to 4.3 W) with a supply voltage of 2.5 V to 5.5 V

The passive devices in state-of-the-art miniaturized switched-mode DC-DC converters are generally integrated by means of on-chip and in-package methods. Nevertheless, the quality is poor-to-moderate, thereby compromising the power-efficiency. In this paper, we propose the miniaturization of the DC-DC converter by means of realizing its passive devices as embedded devices that are printed within a high-density 3D inkjet printed-circuit-board (PCB). We propose a fourth-order stacked LC filter embodying passive components with small values-effectively at no additional cost because they are embedded through 3D-printing. For the inductor and capacitor, we propose to adopt a high-$Q$solenoidal structure and the metal-insulator-metal planar structure, respectively. The proposed filter is printed within the 3D-PCB with a compact 124 mm3volume due to the stacked arrangement. The measured AC attenuation is 21.2 dB at 200 MHz. The filter is further verified by means of computer simulations of a DC-DC buck converter. Simulation results of the converter employing the filter show a low output voltage ripple at 146 mV and a high peak power-efficiency of ~78% at 200 MHz switching frequency with 150 mA load current.

This paper presents a digital current sensor for digitally-controlled current-ripple-based DC-DC buck converters to estimate the instantaneous inductor-current ripple accurately in both the Discontinuous (DCM) and Continuous (CCM) Current Modes. The current sensor employs a proposed dual-mode input multiplexing technique to select an appropriate representation of the pertinent voltage of the switching node$(\boldsymbol{V}_{\boldsymbol{x}})$in any mode, thereby allowing the current to be estimated more accurately compared to that of the prior-art design. The accurate inductor-current ripple information enables the controller to yield output-voltage transient response with small overshoot or undershoot (OS/US) and fast settling time. Benchmarking results using a digitally-controlled current-ripple constant on-time DC-DC buck converter show that the converter employing the proposed sensor achieves$\geq \mathbf{49}{\%}$smaller OS/US and$\geq \mathbf{45}{\%}$faster settling time at the output voltage in both the DCM and the CCM collectively compared with that of the same converter but with the prior-art sensor.

The average power-efficiency of integrated DC- DC converters for Internet-of-Things is generally compromised over a wide load current range. This is because their efficiency is typically severely compromised at light load currents. We present a novel asymmetrical segmented power-stage configuration to improve the average power-efficiency of integrated converters. We achieve this by configuring different power-stage segments with different sizes of power transistors and their inductors, and a circuit to enable the corresponding segment for high power-efficiencies at different load conditions. Specifically, the circuit enables the segment with small-sized power transistors and a large inductor for light-load operations, and conversely, it enables the segment with large-sized power transistors and a small inductor for heavy-load operations. The integrated converter employing our proposed configuration is designed using a CMOS 180 nm process for 2. 5-3.3V input, 1.2 V output, and 50 MHz switching frequency. Simulation results show the proposed converter achieves a high average power-efficiency at ~73% over a wide load current range of 5-200mA. When benchmarked against the competing contemporary designs, the proposed converter features 5-30% higher average power-efficiency over the wide load current range, and >34% higher power-efficiency at 20 mA light load.

This paper presents an ultra-low supply 4-stage output-capacitorless low-dropout (LDO) regulator using a TSMC 40nm process. A novel frequency compensation scheme, which is called feedforward with embedded Miller-RC compensation (FEMRCC), is proposed to guarantee stability throughout the entire load range. The phase margin and gain margin are at least 45.4° and 6.5dB respectively. At a supply voltage of 0.6V, the regulator can support 0 to 150mA of load current. When the load current is stepped from 0 to 150mA, the regulator displays only a 1.5mV undershoot and 0.7mV overshoot, while consuming $39.3 \mu \mathrm{A}$ quiescent current. By utilizing a pseudo-differential cross-coupled pair as the input stage, the LDO regulator achieves a high unity gain bandwidth (UGB) of more than 24MHz. With four gain stages, the minimum DC gain is 55.2dB, ensuring excellent output regulation accuracy. The proposed design is suitable for Internet-of-Things applications with an excellent transient figure-of-merit (FoM) comparable to state-of-the-art designs.

In this paper, a nanowatt comparator for always-on microelectromechanical systems (MEMS) switch wake-up sensor is presented. To achieve continuous event detection with nanowatt ultralow power (ULP) consumption, the comparator building blocks are designed to work in subthreshold region. Various circuit techniques including self-cascode transconductance, feedforward slew rate enhancement are adopted to optimize the circuit performance under nA power consumption. Programmable comparator hysteresis allows the flexibility to conFigure the comparator to operate in different environments. PVT-insensitive voltage/current bias circuits are included to provide stable bias to ensure robust operation across the process corners. The proposed circuit is designed and implemented in a standard 1P8M0.13$-\mu$m CMOS process. The core circuit area is 220$\mu$m× 60$\mu$m. Post layout simulations show that the overall comparator power consumption is in the range of 5. 2-7.8nW under 0. 8V-1.2V supply, the corresponding work bandwidth is up to 6kHz.

Planar air-core inductors come in a variety of geometrical shapes, including in the form of the conventional spiral geometry and novel complex geometries. In the design phase of a system, the inductance of the employed inductor would need to be ascertained. This is usually ascertained by tedious mathematical derivations on a segment-by-segment (inductor) basis or time-consuming computer modeling, and the complexity can become intractable for complex geometries. In this paper, we propose a versatile, yet accurate, vector-based method to ascertain the inductance of planar air-core inductors with virtually any geometry, including novel complex geometry inductors—rather easily. Our proposed method decomposes the inductor segments into vectors, and thereafter utilizes geometric models to compute the inductance in a systematic fashion. We benchmark our proposed method against the conventional electromagnetic field solver simulations to estimate the inductances of six planar inductors ranging from a conventional spiral air-core inductor to that embodying different and complex geometries. On the basis of these six inductor examples, we show that our method is highly accurate with a worst-case error of $\sim 5$% compared to that obtained using conventional electromagnetic field solver. Of particular interest, our modeling for novel complex geometry planar inductors is relatively simple.