This work presents a novel low-power, mixed-signal computing in memory (CIM) architecture for Bayesian inspired inference, targeting edge AI applications requiring energy-efficient uncertainty estimation. Our system integrates a deterministic Binary Neural Network (BNN) with a Bayesian head module implemented using multi-pillar (MP) Spin-Orbit Torque Magnetic RAM (SOT-MRAM) based arrays. The Bayesian head perturbs the output popcount of the BNN by injecting configurable stochastic counts, enabling uncertainty quantification in classification tasks. These perturbations are configurable in ‘flavor’ through a tunable dropout rate and the number of MP cells. A VCO-based ADC converts analog resistive summations into digital counts, which are then combined with the deterministic BNN output. On MNIST and CIFAR-10, the proposed system achieves classification accuracy comparable to state-of-the-art Bayesian approaches while consuming only 19 µW. It achieves a favorable energy efficiency of 53 TOPs/W (18.9 fJ/OPS) for 3-bits and 110 TOPs/W for 2-bits perturbation precision. Uncertainty estimation is validated through controlled domain shifts (e.g., tilted images), showing robust entropy and variance evolution. Notably, the proposed uncertainty estimation requires only 25 perturbation runs, resulting in a total energy cost of just 454 fJ. At this overhead, the Bayesian-inspired model improves reliability by 34.29% compared to the baseline on CIFAR-10. This low-power hybrid analog-digital architecture offers a promising solution for edge applications with embedded confidence metrics.

International audience

GPUs are the prevailing solution to execute high-performance tasks (e.g., machine learning training). As the peak performance of modern GPUs increases with each generation, so does their thermal design power (TDP). Hence, identifying energy bottlenecks in the GPU architecture is crucial to designing more efficient architectures in the future. However, due to the complex proprietary nature of modern GPU architectures, providing a detailed breakdown of the GPU energy consumption is not trivial. The goal of this work is to estimate a lower bound for the energy consumed by data movement and storage in modern GPU architectures, leveraging internal power sensors. We establish a basic energy model for modern GPUs, focused on data movement to/from the hardware-managed caches and software-managed memories. We propose a methodology to calibrate the energy model using microbenchmarks, performance counters, and the internal power sensor. We experimentally calibrate the model on an A100 NVIDIA GPU. Then, we challenge the consistency of the results by cross-validating with modified microbenchmarks with additional instructions. Finally, we use the calibrated energy model to evaluate breakdowns for workloads of increasing complexity (e.g., a ResNet-50 training iteration with different software optimizations). Our results show that data movement dominates the dynamic energy consumption of the GPU (up to 84%), with DRAM accesses being the main contributor.