Natalia Cherezova

VLDB 2026 Research / reviewers in the wild / expert

dblp:336/4271 · DBLP profile ↗

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8ranked-venue papers

3as first author

8since 2021 · last 2026

0000-0001-9181-5544ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 8 · 3 first-author · 8 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021

Year	Publication	Venue	Position
2026	Scalable Reliability Assessment of Vision Transformers on Systolic Arrays via Fault Propagation Analysis Natalia Cherezova, Artur Jutman, Maksim Jenihhin	IOLTS	1
2026	Special Session: Reliability Assessment of DNN Models and Inference on Systolic Arrays Natalia Cherezova, Salvatore Pappalardo, Annachiara Ruospo, Bastien Deveautour, Lorenzo Fezza, Artur Jutman, Ernesto Sánchez 0001, Alberto Bosio, Matteo Sonza Reorda, Maksim Jenihhin	VTS	1
2025	RL-Agent-based Early-Exit DNN Architecture Search Framework abstract This paper introduces a Reinforcement Learning (RL)-based framework for optimizing early-exit configurations in Deep Neural Networks (DNNs). By integrating RL with BranchyNet-inspired architectures, the framework dynamically determines optimal early exit placements and confidence thresholds, balancing inference time, energy consumption, and accuracy. Key contributions include an early-exit DNN architecture search, an RL-driven threshold optimization process during training, and a design-space exploration open-source framework. Experiments on models such as ResNet-18, VGG-16, and AlexNet, using benchmarks like CIFAR-10 and MNIST, reveal significant reductions in inference time (up to 69.7x) and power consumption while keeping accuracy drop within 1-2%. This work demonstrates that dynamic early-exit strategies can enhance DNN efficiency while maintaining performance, paving the way for resource-constrained applications. Mahdi Taheri, Parth Patne, Natalia Cherezova, Ali Mahani 0001, Christian Herglotz, Maksim Jenihhin	DDECS	3
2025	European Test Symposium Teams: an Anniversary Snapshot abstract The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing. Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, Iulia Stefan, Ovidiu Stan, Cosmina Corches, Zebo Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, Po-Yao Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi 0002, Stefano Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. D. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, Patrick Girard 0001, Marcello Traiola, Arnaud Virazel, Fernando Santos 0001, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Veiras Bolzani, Milos Krstic, Marko S. Andjelkovic, Fabian Vargas 0001, Grigor Tshagharyan, Gurgen Harutunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, Anurup Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zainalabedin Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand	ETS	4
2025	Adaptive Fault Resilience for Early-Exit DNNs abstract Dynamic Deep Neural Networks (D2NNs) with early exits have emerged as an effective architecture for reducing computational overhead and inference latency. While fault tolerance in their static counterparts has been extensively studied, the dynamic models remain largely unexplored for enhanced reliability. This paper addresses that gap by developing Bayesian optimization algorithms to determine optimal early-exit confidence thresholds for enhanced fault resilience in dynamic DNNs. We present a reliability assessment of BranchyNet models compared to their static counterparts across three state-of-the-art architectures, introducing random bit flips (up to 0.01% of total model parameters) across 11 logarithmically increasing Bit Error Rates (BERs). The study analyzes fixed and adaptive thresholds that dynamically adjust considering the estimated fault rates. The results demonstrate that BranchyNet models exhibit greater fault resilience, preserving accuracy even at BER levels up to 2× higher than those tolerated by static models, with adaptive thresholds providing the strongest resilience. By combining exit threshold tuning with multiple inference pathways, early-exit DNNs offer a practical means to mitigate radiation-induced soft errors in hardware deployments. Rama Mounika Kodamanchili, Natalia Cherezova, Mahdi Taheri, Maksim Jenihhin	ITC-Asia	2
2025	Architectural Exploration and Implementation of CERN LHC Trigger Algorithm With FPGA abstract The upcoming high-luminosity upgrade of the Large Hadron Collider (LHC) at CERN will increase data rates to values far exceeding the capabilities of software-based processing systems. As a result, new methods are required to efficiently extract scientifically valuable information from the massive data streams produced by the LHC’s particle detectors. This article discusses the design of the tau lepton trigger algorithm using the field-programmable gate array (FPGA) technology. Given its complexity and demanding technical requirements, realizing the algorithm in FPGA is a challenging task. This article details the algorithm development using high-level synthesis (HLS), a technique to generate hardware descriptions from the C++ code. We discuss architectural solutions and optimizations explored during the design process, including algorithm partitioning and pipelining, optimization of pipeline stages, floorplanning, and probing of implementation strategies. The performed design space exploration helped to improve latency, solve area-related issues, and reduce routing congestion, enabling implementation of tau lepton trigger on FPGA. Sergei Devadze, Christine Elizabeth Nielsen, Natalia Cherezova, Dmitri Mihhailov, Peeter Ellervee	IEEE Trans. Very Large Scale Integr. Syst.	3
2024	AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators abstract Multiplication is the most resource-hungry operation in the neural network’s processing elements. In this paper, we propose an architecture of a novel adaptive fault-tolerant approximate multiplier tailored for ASIC-based DNN accelerators. AdAM employs an adaptive adder relying on an unconventional use of the leading one position value of the inputs for fault detection through the optimization of unutilized adder resources. The proposed architecture uses a lightweight fault mitigation technique that sets the detected faulty bits to zero. The hardware resource utilization and the DNN accelerator’s reliability metrics are used to compare the proposed solution against the triple modular redundancy (TMR) in multiplication, unprotected exact multiplication, and unprotected approximate multiplication. It is demonstrated that the proposed architecture enables a multiplication with a reliability level close to the multipliers protected by TMR utilizing 63.54% less area and having 39.06% lower power-delay product compared to the exact multiplier. Mahdi Taheri, Natalia Cherezova, Samira Nazari, Ahsan Rafiq, Ali Azarpeyvand, Tara Ghasempouri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin	ETS	2
2024	Heterogeneous Approximation of DNN HW Accelerators based on Channels Vulnerability abstract Since Deep Neural Networks (DNNs) gracefully withstands approximation due to its inherent redundancy, Approximate Computing (AxC) can be applied to reduce power consumption and execution time. In the literature, several works adopted the AxC paradigm to DNNs in the form of quantization, precision reduction, pruning, and functional approximation. Despite the promising results demonstrated so far, most of the existing works have applied homogeneous AxC techniques, meaning that the same degree of approximation has been applied to the entire DNN. However, different DNN components (i.e., channels, filters, layers, neurons) have different resiliency levels. This paper presents a framework for applying heterogeneous AxC to DNN hardware accelerators. The framework is based on the identification of channel resilience and applying a tailored degree of approximation per channel. Preliminary results carried out on the LeNet-5 model show that by using the proposed framework it is possible to decrease resource utilization by 65.2% and power consumption by 53.4% at the cost of a marginal drop of accuracy from 98.87% to 98.03%. Natalia Cherezova, Salvatore Pappalardo, Mahdi Taheri, Mohammad Hasan Ahmadilivani, Bastien Deveautour, Alberto Bosio, Jaan Raik, Maksim Jenihhin	VLSI-SoC	1