Bayesian inference is one method of statistical inference in machine learning. It predicts the probability that a given test belongs to a certain class and is widely used in various applications such as medical diagnosis, spam classification and fraud detection. The conventional binary architecture of computing the posterior probability is inefficient in practical implementation, which is involved in multiplication, addition and division operations. Recently, it has been shown that simple Muller C-elements, the asynchronous logic units, can perform stochastic Bayesian inference motivated by its truth table when the data is encoded as the bit-stream. The Bayesian inference machine is therefore implemented with low hardware cost. However, such an architecture is employed to compute the posterior probability of two classes only. This brief presents two stochastic circuit designs for computing the weighted ratio with multiple weights for generalized multi-class Bayesian machines. The first design is mainly based on the JK flip flop and multiplexers. The second approach is to construct the finite state machine (FSM) by manipulating the correlation between the input bit-streams. The FSM-based design requires fewer random number sources (RNSs) as compared to the JK flip flop-based implementation. These facts lead to a reduction of hardware area and energy. Simulation results show that the accuracy of the proposed JK flip flop-based and FSM-based designs is almost the same in the tested data sets. As compared to the traditional binary design, the circuit area of the proposed stochastic design is improved by$96\%$at least in the cases of three and four classes. The consumed energy per operation is reduced by$58.1\%$at least in the cases of three and four classes.