With the end of Moore’s Law, multi-chiplet systems have emerged as a promising solution featuring heterogeneity across chiplets, interconnects and packaging. Existing simulators lack support for such multi-level heterogeneity, making accurate architectural exploration difficult. We propose Hetero-ChipletSim (HCS), a simulation methodology that directly integrates heterogeneous chiplet models while incorporating die-to-die(D2D) interconnect and packaging effects, enabling fast and accurate evaluation of multi-chiplet systems. Sensitivity analysis provides insights into design trade-offs under heterogeneous integration.

The rising cost and complexity of cutting-edge process nodes have impeded large monolithic System-on-Chip to follow Moore’s Law, forcing chip designers to embrace Multi-Chiplet architectures. Multi-chiplet designs achieve cost reduction while maintaining near-monolithic performance by disaggregating a large die into smaller chiplets and integrating them through advanced packaging. The payback of this Disaggregation-Integration paradigm critically depends on the efficacy of chiplet Partition and Placement framework. However, existing frameworks fail to harness the potential merits offered by Partition-Placement Co-Optimization. Serving as an input provider for placement, partition phase typically adjusts block-to-die assignments to guide subsequent placement. This sequential dependency implies an inherent Partition-Placement (P2P) Inconsistency problem: solutions optimal solely in partition or placement may finally cause an inferior solution. Hence, this paper proposes P2P-Chiplet, a Partition-Placement Co-Optimization framework for multi-chiplet designs. Firstly, an optimized ACG structure, named as HeteroACG, is introduced to aggregate topological partition and physical placement optimization spaces. Then, the sequential partition-placement flow is decomposed into interleaved fine-grained epochs and an alternating progressive optimization strategy is employed to preserve P2P Consistency and bring better co-optimized solutions. Finally, experimental results show that, compared with existing chiplet partition-placement frameworks, our proposed P2P Chiplet notably mitigates potential performance bottlenecks while effectively reducing costs within acceptable overhead.

Coarse-Grained Reconfigurable Architecture (CGRA), especially the one with multiple parallelized Processing Element Arrays (PEA), possesses flexible programmability and high parallel computational efficiency, which relies upon an efficient memory architecture to deliver the corresponding computing power. Multi-PEA oriented CGRA allows for mapping various applications and thus demands a flexible memory to adapt to the ever-changing workloads, whose parallel access also requires an efficient multi-port memory. However, the existing memory designs for CGRA are hard to satisfy those requirements since conventional rigid memories fail to provide the desired flexibility due to fixed structure, and traditional multi-port designs are impractical due to large overhead. Therefore, this paper proposes a hardware/software (HW/SW) hybrid reconfigurable multi-port memory architecture (RMP-MEM) with an instructive analysis for the multi-PEA oriented CGRA. RMP-MEM supports adaptive memory partition and programmer-defined access modes to adapt the different features of memory accesses. Also, RMP-MEM achieves an efficient multi-port implementation by a partially shared mechanism. Furthermore, the microarchitecture of RMP-MEM is optimized multi-directionally, resulting in a significant performance gain. The experimental results indicate that RMP-MEM reduces the parallel access latency by 81.1% and exhibits 28.3% energy efficiency improvement compared to prior designs.