Demo Data from VLDB 2026 / reviewers in the wild / expert
Tim Oberschulte
dblp:339/8786
· DBLP profile ↗
2ranked-venue papers
2as first author
2since 2021 · last 2025
0000-0001-6334-4458ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Hardware reliability and fault tolerance · 52% Integrated circuit design · 29% Electronic design automation · 16% |
Topics — the 7 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › digital circuit design
arithmetic circuit design |
0.9 | 1 | 2025 | RRNS Arith Lib - An Open-Source Redundant Residue Number System Arithmetic VHDL Library · FPGA 2025 |
Hardware reliability and fault tolerance
error detection and correction |
0.9 | 1 | 2025 | RRNS Arith Lib - An Open-Source Redundant Residue Number System Arithmetic VHDL Library · FPGA 2025 |
Hardware reliability and fault tolerance › arithmetic codes
redundant residue number system |
0.9 | 1 | 2025 | RRNS Arith Lib - An Open-Source Redundant Residue Number System Arithmetic VHDL Library · FPGA 2025 |
Integrated circuit design
residue number system arithmetic |
0.9 | 1 | 2025 | RRNS Arith Lib - An Open-Source Redundant Residue Number System Arithmetic VHDL Library · FPGA 2025 |
Electronic design automation › hardware verification and test
fault detection |
0.7 | 1 | 2023 | Fault Detection on Multi COTS FPGA Systems for Physics Experiments on the International Space Station · FPGA 2023 |
Hardware reliability and fault tolerance
radiation effects |
0.7 | 1 | 2023 | Fault Detection on Multi COTS FPGA Systems for Physics Experiments on the International Space Station · FPGA 2023 |
Hardware reliability and fault tolerance › soft errors
single-event upset mitigation |
0.7 | 1 | 2023 | Fault Detection on Multi COTS FPGA Systems for Physics Experiments on the International Space Station · FPGA 2023 |
Methods — techniques the papers use, named apart from their topics
VHDL library · 0.9triple modular redundancy · 0.7fault injection · 0.7double modular redundancy · 0.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | RRNS Arith Lib - An Open-Source Redundant Residue Number System Arithmetic VHDL LibraryabstractA Residue Number System (RNS) represents integers through a set of residues obtained by integer division using a predefined set of pairwise coprime moduli. RNS is well-known for enabling efficient carry-free arithmetic and representing large numbers with multiple shorter numerical values. By incorporating additional moduli, the system can be extended into an over-determined Redundant Residue Number System (RRNS), introducing redundancy that facilitates the detection and correction of bit errors. Tim Oberschulte, Enno Sievers, Holger Blume |
FPGA | 1 |
| 2023 | Fault Detection on Multi COTS FPGA Systems for Physics Experiments on the International Space StationabstractField-programmable gate arrays (FPGAs) in space applications come with the drawback of radiation effects, which inevitably will occur in devices of small process size. This also applies to the electronics of the Bose Einstein Condensate and Cold Atom Laboratory (BECCAL) apparatus, which is planned to operate on the International Space Station for several years. A total of more than 100 FPGAs distributed in the setup will be used for high-precision control of specialized sensors and actuators at nanosecond scale. Due to the large amount of devices in BECCAL, commercial off-the-shelf (COTS) FPGAs are used which are not radiation hardened. In this work, we detect and mitigate radiation effects in an application specific COTS-FPGA-based communication network. For that redundancy is integrated into the design while the firmware is optimized to stay within the FPGA's resource constraints. A redundant integrity checker module is developed which can notify preceding network devices about data and configuration bit errors. The firmware is evaluated by injecting faults into data and configuration registers in simulation and real hardware. The FPGA resource usage of the firmware is cut down by more than half, enabling the use of double modular redundancy for the switching fabric. Together with the triple modular redundancy protected integrity checker, this combination fully prevents silent data corruptions in the design as shown in simulations and by injecting faults in hardware using the Intel Fault Injection FPGA IP Core while staying in the resource limitation of a COTS FPGA. Tim Oberschulte, Jakob Marten, Holger Blume |
FPGA | 1 |