In Resistive Random Access Memory (RRAM) based compute-in-memory designs, the column current readout circuits still consume too much area and power overhead, even if plenty of methods have been proposed to optimize the circuits. To alleviate this problem, this paper presents a novel current readout circuit to sense multiply-and-accumulate (MAC) result of RRAM array. Specifically, the circuit first integrate the stabilized and proportionally mirrored MAC current on a small capacitor until it fires, then sample the integration time with a set of reference signals with different carefully designed delays, and finally code the sampled result into a digital value. The proposed readout circuit has fine stability due to simple and determined relationship among the inputs, the RRAM cells’ states, and the MAC current. Meanwhile, the proposed design can achieve accurate MAC result readout at low resistance switching ratios, for it employs a current compensation circuit to remove background current caused by high resistance state RRAM cells. Our design is implemented using 28nm CMOS technology with a read latency of 2.8ns and an area occupation of 267μm2/channel, which is 12.5% and 89% less than state of the art design. Its power consumption, 0.092mW/channel, is also less than most counterpart designs.

The RRAM-based accelerators have become very popular candidates for neural network acceleration due to they perform matrix-vector multiplication in-memory with high storage density and low latency. Many related works have used fixed-precision quantization to achieve the model compression and enhance the tolerance of process variation, but these methods still suffer a large accuracy degradation and poor robustness to nonideal effects. In this work, we propose a crossbar-aware mixed-precision quantization scheme, which enables to search for the optimal precision of each part of the network as a way to improve the accuracy and robustness to noise. First, we introduce a group quantization strategy that can flexibly adjust the group size dynamically according to the crossbar size. Then, we propose a detailed mixed-precision search flow to search for the optimal precision set of the network. Finally, we give a noise injection adaption training method to enhance the tolerance of noise. Experimental results show that our proposed method can improve inference accuracy by at least 2.04% compared to the fixed-precision quantization under the same resource cost. The searched architecture with the highest accuracy most accurate (MA) could achieve an accuracy of 92.39% and a resource saving of 93.30% compared to the full precision model. The searched architecture with the biggest resource savings most efficient (ME) could achieve an accuracy of 91.11% and a resource saving of 95.57% compared to the full precision model. And, the average precision of the ME mixed-precision architecture is only 1.4 bits. Besides, the results show the mixed-precision network with noise adaption training is more robust to noise than the fixed-precision network with noise adaption training.

Recent years, several memristor-based neuromorphic processing chips have been proposed. However, there is few architectures to consider the cascading problems, and the scalability is not strong while dealing some tasks. To address this issue, we present a memristor-based cascaded method with some basic computation unit, several neural network processing chips can be cascaded by this means to improve the processing capability of the dataset. Compared with VGGNet and GoogLeNet, the proposed cascaded framework can achieve 93.54% Fashion-MNIST accuracy under the 4.15M parameters. Extensive experiments are conducted show that the circuit simulation results can still provide a high recognition accuracy, the recognition accuracy loss after circuit simulation can be controlled at around 0.26%.

With the rapid development of VLSI industry, the research of intelligent applications moves towards IoT edge computing. While the power consumption and area cost of deep neural networks usually exceed the hardware limitation of edge devices. In this paper, we propose a low-power neural network architecture to address such problem. We simplify the current popular convolutional neural networks structure, and utilize the memristor crossbar to store weights to execute convolution operation in parallel, and we present the spiking convolutional neural networks. At the same time, we proposed a performance metrics V to help provide design guidelines for choosing the parameters of the network.

In this study, we propose an ultra-fast compliance current circuit for ReRAM electrical characterization. The circuit utilizes high speed components with low propagation delay and can reduce the overall response time to nanosecond level. Both simulated and measured results demonstrate that our proposed compliance current circuit possesses response time of ~100ns, and thus can effectively reduce the hard breakdown possibility under the large compliance setting during the ReRAM characterization process.

In this study, we explore the impact of active areas on electrical characteristics of practical TiO2based memristors. Initially, it is experimentally demonstrated that high resistive state is independent of active areas, while low resistive state is in proportion to the dimensions of active cells. We then argue that these observations could stem from the filamentary formation and rupture within the TiO2active cores. Finally, we investigate the dependence of I-V characteristics on active cell size and present measured results that are in good agreement with theoretical analysis.

Nanoscale resistive switching devices are nowadays widely employed in applications of storage, logic and computing. The switching mechanism of metal oxide based devices is normally assumed to be the filamentary formation and rupture within the devices' active cores but the origin of filaments growth is still controversial. Previous research has already demonstrated that initial filamentary states could significantly affect the devices' switching dynamics and final resistance distributions. Here we demonstrate the relation between pristine resistive states and distribution of filaments via modeling the switching dynamics by utilizing a current percolation circuit. We show that devices with identical initial resistive states could attain distinct plausible filamentary distributions and correspondingly manifest very dissimilar switching dynamics even when biased with similar stimuli.

Channel mismatches of time-interleaved analog-to-digital converters (TIADC) would result in significant decline of dynamic performance, especially in signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR). However, as one kind of the channel mismatches, nonlinearity mismatch has not been widely investigated. In this paper, we analyze the characteristics of nonlinearity mismatch and its influence on TIADC's dynamic performance by using polynomial model. A foreground estimation method is proposed and evaluated. The simulation results demonstrate that the proposed method can perform fine estimation accuracy. Furthermore, we investigate the relationship between the estimation accuracy and the sample length, and the result is helpful to configure an appropriate sample length according to different performance requirements.