Statistical analysis of computations per unit energy in processors over the last 30 years is given that illustrates a sharp reduction in the rate of energy efficiency improvements over the last several years resulting in the formation of an asymptotic “wall” with our dataset; we use the measure of giga multiply accumulates per Joule. We have developed an energy model which takes into account the realities of scaling, specifically for asynchronous systems. Studies of an energy efficient asynchronous pipeline show fabricated results of 17 Giga Operations per Joule in 0.6 μm at subthreshold when fully pipelined, and simulations at a more modern 65 nm process show a further order of magnitude improvement on that.

We present the field programmable array of analog and digital devices (FPAADD) as a novel implementation of a field programmable mixed-signal array (FPMA). The FPAADD is a hybrid combination of a field programmable analog array (FPAA) and a field programmable gate array (FPGA). Unlike other FPMAs where the FPGA and FPAA portions are kept separate, this architecture closely integrates the two in a fine-grained interleaved array. Instead of using hard-coded data converters, the FPAADD synthesizes data converters out of its reconfigurable fabric. The analog and digital portions share a common global interconnect. Floating gate (FG) transistors are used as the switch and memory elements of the chip, providing better switch performance and power over traditional static random-access memory-based approaches. The precise programmability of the FG switches also allows for computation to take place in the interconnect. These key differences make the FPAADD much more general purpose than previous FPMA architectures. The FPAADD consists of 27 × 8 array of 108 digital and 108 analog tiles and peripheral circuitry on 5 × 5 mm2die fabricated in a 0.35- μm CMOS process, and contains more than 130 000 FG transistors.

We have designed and built the first commercially available all-analog adaptive beamforming integrated circuit utilizing a dual microphone array. Beamforming performs spatial filtering by exploiting time-of-arrival differences between microphones. Our analog implementation has the advantage of using very little power which is important in portable, battery-powered devices. Rather than optimize parameters for a single filter as in a standard adaptive FIR filter used in conventional beamformers, our implementation selects among multiple filters each pre-programmed to provide various different spatial-filter patterns.

Large-scale field programmable analog array (FPAA) ICs have made analog and analog-digital signal processing techniques accessible to a much wider community. Given this opportunity, we present in this paper a framework for considering analog signal processing techniques for low-power, portable systems. These techniques have become more important given the recent recognition of the power-efficiency wall for commercial digital ICs. The discussion focuses on the framework technique required to enable analog-digital signal processing techniques. A framework is needed to enable system designers to directly develop applications into these approaches that includes considering power consumed, system complexity/area, as well as other commercial metrics. A key part of this discussion is evolving existing Simulink FPAA design tools to work with this framework such that users have a similar experience one expects with digital system design, as well as model closely experimental data at a high-level framework. The result of these techniques is pulling analog computation towards the system level development as seen in digital system design over the last 30 years.

We present the successful application of reconfigurable Analog-Very-Large-Scale-Integrated (AVLSI) circuits to motion planning for the AmigoBot robot. Previous research has shown that custom application-specific-integrated-circuits (ASICs) can be used for robot path planning. However, ASICs are typically fixed circuit designs that require long fabrication times on the order of months. In contrast, our reconfigurable analog circuits called Field Programmable Analog Arrays (FPAAs) implement a variety of AVLSI circuits in minutes. We present experimental results of online robot path planning using FPAA circuitry, validating our assertion that FPAA-based AVLSI design is a feasible approach to computing complete motion plans using analog floating-gate resistive grids. We demonstrate the integration of FPAA hardware and software with a real robot platform and hardware in the loop simulations, present the trajectories developed by our planner and provide analysis of the time and space complexity of our proposed approach. The paper concludes by formulating metrics that identify domains where analog solutions to planning may be faster and more efficient than traditional, digital robot planning techniques.

While the development of reconfigurable analog platforms is a blossoming field, the tradeoff between usability and flexibility continues to be a major barrier. Field Programmable Analog Arrays (FPAAs) built with translinear elements offer a promising solution to this problem. These FPAAs can be built to use previously developed synthesis procedures for translinear circuits. Furthermore, large-scale translinear FPAAs can be built using floating-gate transistors as both the computational elements and the reconfigurable interconnect network. An FPAA built using Multiple Input Translinear Elements (MITEs) has been designed, fabricated in 0.35 μ m CMOS, and tested. These devices have been programmed to implement various circuits including multipliers, squaring circuits, RMS-to-DC converters, and filters. In addition, synthesis, place-and-route, and programming tools have been created in order to implement a reconfigurable system where the circuits implemented are described only by equations. The continued development of translinear FPAAs will lead to a reconfigurable analog system that allows for a large portion of the design to be abstracted away from the user.

With the rapid increase in size and complexity of analog systems being implemented on field-programmable analog arrays (FPAAs), the need for synthesis tools is becoming a necessity. In this paper, we present Sim2spice, a tool that automatically converts analog signal-processing systems from Simulink designs to a SPICE netlist. This tool is the top level of a complete chain of automation tools. It allows signal-processing engineers to design analog systems at the block level and then implement those systems on a reconfigurable-analog hardware platform in a matter of minutes. We will provide detailed descriptions of each stage of the design process, elaborate on a custom library of analog signal-processing blocks, and demonstrate several examples of systems automatically compiled from Simulink blocks to analog hardware.

This paper presents preliminary results of a mobile manipulator robot tasked to play the classic Towers of Hanoi game. We first discuss the control algorithms necessary to enable necessary game-playing behavior and provide results of implementing our methodology in a high fidelity 3D environment. After attaining success in the simulation environment, we provide results on implementation of the same control software using physical robot hardware. Additionally, preliminary analysis for implementing analog Proportional-Integral-Derivative (PID) control on this platform using a floating-gate based reconfigurable analog IC is explored. Using this concept of floating gate analog arrays for control enables off-loading of the processing, which could be helpful for real-time implementation of robot behavior.

This paper presents an on-chip system with digital serial peripheral interface (SPI) interface that enables accurate programming of floating gate arrays at a high speed. The main component allowing this speedup is a floating point current measuring analog-to-digital convertor (ADC). The ADC comprises a wide range logarithmic transimpedance amplifier (TIA) followed by a linear ramp ADC. The TIA operates over seven decades of current going down to sub-pA levels. It incorporates an adaptive biasing scheme to save power. The topology provides a relatively temperature independent measurement of the floating-gate voltage. The TIA-ADC combination operates over six decades at a thermal noise limited accuracy of 9.5 bits when average conversion time is around 500 μs. The system features level-shifters and selection circuitry at the periphery of the floating gate array, current-steering digital-to-analog converters (DACs) to set gate and drain voltages, and SPI for a microprocessor or field-programmable gate array (FPGA). Algorithms using either pulse-width modulation or drain voltage modulation can be implemented on this platform. We present data for this system from 0.5 μm AMI and 0.35 μ m TSMC processes.

This paper presents a vector-matrix multiplier (VMM), which can be easily implemented on a field programmable analog array (FPAA). This VMM can be synthesized directly into the switch-fabric of the FPAA, allowing for incredibly dense matrix operations. As an important aspect of this system, we utilize a complete chain of tools that compile the VMM design from Simulink blocks onto the FPAA hardware. We also demonstrate the usefulness of the analog VMM by relying on it to perform two common signal processing tasks.

A neuromorphic analog chip is presented that is capable of implementing massively parallel neural computations while retaining the programmability of digital systems. We show measurements from neurons with Hopf bifurcations and integrate and fire neurons, excitatory and inhibitory synapses, passive dendrite cables and central pattern generators implemented on the chip. This chip provides a platform for not only simulating detailed neuron dynamics but also using the same to interface with actual cells in applications like a dynamic clamp. The programmability is achieved using floating gate transistors with on-chip programming control. The switch matrix for interconnecting the components also consists of floating-gate transistors. Massive computational area efficiency is obtained by using the reconfigurable interconnect as synaptic weights.

A floating-gate, cross-bar switch matrix with a novel programming method is presented. Single-polysilicon floating-gate transistors are used to hold a “bit” state programmed with short-channel pFET devices that demonstrate hot-electron injection over a large current range. Hot-electron injection modeling in pFETs is contrasted across various channel lengths and bias currents. Circuit design and physical layout are discussed, and characterization data is presented from a matrix fabricated in a 0.5 μm, scalable CMOS process available through MOSIS.

Analog circuits and systems research and education can benefit from the flexibility provided by large-scale Field Programmable Analog Arrays (FPAAs). This demonstration will present visitors with the hardware and software infrastructure supporting the use of a family of floating-gate based FPAAs being developed at Georgia Tech. A picture of the programming and control hardware that will be demonstrated is found in Figure la. Figure lb shows the software flow that will be demonstrated. The infrastructure is compact and portable and provides the user with a comprehensive set of tools for custom analog circuit design and implementation. The infrastructure includes the FPAA integrated circuit (IC); discrete analog to digital converters (ADC), digital to analog converters (DAC) and amplifier ICs; a 32-Bit ARM based microcontroller (μC) for interfacing the FPAA with a laptop computer; and Matlab and targeting software. The FPAA hardware communicates with Matlab over a Universal Serial Bus (USB) connection. The USB connection also provides the hardware's power. The software tools in the demonstration include three major systems: a Matlab Simulink FPAA program, a SPICE to FPAA compiler called GRASPER, and a visualization tool called RAT. Figure 2 shows a block diagram of the Programming and Control board and demonstration setup.

Analog circuits and systems research and education can benefit from the flexibility provided by large-scale Field Programmable Analog Arrays (FPAAs). This paper presents the hardware and software infrastructure supporting the use of a family of floating-gate based FPAAs being developed at Georgia Tech. This infrastructure is compact and portable and provides the user with a comprehensive set of tools for custom analog circuit design and implementation. The infrastructure includes the FPAA IC, discrete ADC, DAC and amplifier ICs, a 32-Bit ARM based microcontroller for interfacing the FPAA with the user's computer, and Matlab and targeting software. The FPAA hardware communicates with Matlab over a USB connection. The USB connection also provides the hardware's power. The software tools include three major systems: a Matlab Simulink FPAA program, a SPICE to FPAA compiler called GRASPER, and a visualization tool called RAT. The hardware consists of two custom PCB designs which include a main board used to program and control an FPAA IC and an FPAA IC adaptor board used to interface a QFP packaged FPAA IC with the 100 pin ZIF socket on the main programming and control board.

We present CMOS electronics for optical sensing of diffraction based micromachined microphone. Peak detector and track and hold circuits are used for continuous time approach with only 58 μA of current for 65dB peak SNR (lPa at 1kHz). We also present a 1-bit sigma delta interface ADC for directly digitizing the signal for digital processing with 63 μA of current for 62dB peak SNR (lPa @ 1kHz). The electronics are designed in 0.35um standard digital CMOS process with reduced supply of 1.5Volts. All the analog front end circuits operate in weak inversion with rail-to-rail wide input linear range.

This paper demonstrates a single transistor synapse that stores a weight in a non-volatile manner, computes a biological EPSP, and also demonstrates biological learning rules such as LTP, LTD and STDP. It also describes a highly scalable architecture of an array of synapses that can implement the described learning rules. Parameters for weight update in a 0.35μm process were extracted and used to predict changes in weight based on the time difference between pre-synaptic and post-synaptic spike times.

Multiple-Input Translinear Elements (MITEs) are a powerful tool for implementing translinear networks. Large-scale implementations of translinear networks have been plagued by mismatch when implemented in standard CMOS processes. The floating-gate MITE approach allows for adjustments to MITE elements post-fabrication to compensate for process-induced mismatch. In order to demonstrate this approach, a 2D-vector magnitude circuit and a cube root circuit have been synthesized to a reprogrammable architecture on a 0.35μm, commercially available, CMOS process. Sources of mismatch were predicted, identified, and then measured and compensated in silicon.

This paper demonstrates a computational image sensor capable of implementing compressive sensing operations. Instead of sensing raw pixel data, this image sensor projects the image onto a separable 2-D basis set and measures the corresponding expansion coefficients. The inner products are computed in the analog domain using a computational focal plane and an analog vector-matrix multiplier (VMM). This is more than mere postprocessing, as the processing circuity is integrated as part of the sensing circuity itself. We implement compressive imaging on the sensor by using pseudorandom vectors called noiselets for the measurement basis. This choice allows us to reconstruct the image from only a small percentage of the transform coefficients. This effectively compresses the image without any digital computation and reduces the throughput of the analog-to-digital converter (ADC). The reduction in throughput has the potential to reduce power consumption and increase the frame rate. The general architecture and a detailed circuit implementation of the image sensor are discussed. We also present experimental results that demonstrate the advantages of using the sensor for compressive imaging rather than more traditional coded imaging strategies.

The concept of learning digital hardware is presented here. A proof of concept of a circuit that can arbitrarily control the current, and thus the switching speed and power consumption, of a digital circuit is given. This control of current is directly tuned by the feedback from the digital circuit itself, thus a learning digital computer. An argument for a completely new paradigm in digital computing follows whereby an entire system of learning digital circuits is proposed.

In this paper, we present a Spiking Neural Network (SNN) architecture that incorporates Integrate-and-fire (IF) type neurons and floating-gate transistors (FGTs) to store the synaptic weights. Compactness of the network has been the major target throughout the design. We believe that a CrossNet architecture lends itself very well to satisfy this goal. The synaptic weights are updated locally according to an approximation of Spike-Timing-Dependent Plasticity (STDP) rule. While the computations are performed internally in the analog domain the network is interfaced with a digital Address-Event-Representation (AER) to achieve robust off-chip communication. The operation of the array is described and selected simulations with 65 nm CMOS are shown.

A method to approximate nFET passgate resistance using the compact EKV model is presented. The model picks a mobility that has a greater effect on channel current than higher-order MOS effects in order to approximate the worst-case current over a drain-source voltage range. The model is compared to data taken from an IC that was fabricated in a 0.5 mum, scalable CMOS process available through MOSIS.

Motivated by the unwillingness to accept the worst-case timing constraint that synchronous logic imposes, and additionally motivated by finding a supply voltage scaling scheme for datapath circuits that is unconstrained by timing errors in memory elements, the authors have built an asynchronous datapath that is embedded seamlessly into a synchronous register file. This paper will show that not only does asynchronous arithmetic logic exhibit many characteristics that allow it to be inherently lower power, but it is significantly faster than any synchronous counterpart and is a perfect candidate technology for datapath acceleration. Further, novel circuits are presented that allow asynchronous datapath units to be embedded in a synchronous environment with little overhead while the dual-rail asynchronous encoding scheme is successfully converted with equally low overhead. The authors have built a test chip being fabricated at the time of publication. The circuits on this chip will be discussed and simulation results given showing this design to be both energy and performance efficient when compared to other known datapath designs.

The Reconfigurable Smart Sensory Chip (RSSC) is a powerful tool for fast prototyping sensory microsystems. Innovative design ideas can be quickly realized and tested in hardware without doing time-consuming and expensive silicon fabrication. The RSSC is a large-scale floating-gate based IC containing 8 universal sensor interface blocks, each of which can be configured for voltage sensing, capacitive sensing, or current sensing, and 28 configurable analog blocks. The outputs of the interface circuits can be multiplexed out in a time-division sequence or can be routed to the configurable analog blocks for further analog signal processing or data conversion. With more than 50,000 programmable elements and on-chip programming circuitry, RSSC is an extremely powerful tool to develop and test a great variety of smart sensory microsystems in minutes.

A 16 × 16 programmable analog radial-basis-function (RBF) based classifier is demonstrated. The distribution of each feature is modeled by a Gaussian function, which is realized by a proposed floating-gate bump circuit having bell-shaped transfer characteristics. The maximum likelihood, mean, and variance of the distribution are stored in floating-gate transistors and are independently programmable. By cascading these floating-gate bump circuits, the overall transfer characteristics approximate a multivariate Gaussian distribution with a diagonal covariance matrix. An array of these circuits constitutes a compact RBF-based classifier. When followed by a winner-take-all circuit, the analog classifier can implement vector quantization. Automatic gender identification is implemented on a 16 × 16 analog vector quantizer chip as one possible audio application of this work. The performance of the analog classifier is comparable to that of digital counterparts. The proposed approach can be at least two orders of magnitude more power efficient than the digital microprocessors at the same task.

This paper discusses the application of a computational image sensor, capable of performing separable 2-D transforms on images in the analog domain, to compressive sensing. Instead of sensing and transmitting raw pixel data, this image sensor first projects the image onto a separable 2-D basis set. The inner products computed in these projections are computed in the analog domain using a computational focal-plane and a computational analog vector-matrix multiplier. Since this operation is performed in the analog domain, components such as the analog-to-digital converters can be taxed less when a only subset of correlations are performed. Compressed sensing theory prescribes the use of a pseudo-random, incomplete basis set, allowing for sampling at less than the Nyquist rate. This can reduce power consumption or increase frame rate.

In this paper, we describe the bifurcations occurring in a silicon neuron with one sodium and one potassium channel. The channels are designed to model the physics of ion flow in actual biological channels instead of modeling a particular set of equations. We show a pair of subcritical Hopf-bifurcation with increase in current stimulus which is characteristic of class 2 excitability in Hodgkin-Huxley neurons. Theoretical analysis of the bifurcations lead to conditions for designing and biasing the circuit. The circuit is very compact, comprising six transistors and three capacitors, lending itself to easy integration. The parameters are set using floating-gate transistors and can be programmed as desired. We hope to study more complicated dynamics of large networks of these neurons, a task which might be beyond a typical digital computer.

This paper presents our programmable floating-gate dendrite model based upon our transistor channel models. We are developing a flexible, low-power, real-time computational engine for studying, understanding, and implementing neural computation. Here we present a systematic study of the dynamics seen in this silicon model, emphasizing the connection to conventional neurobiological modeling of dendrites. These results provide a foundation for future work on larger systems.

This paper describes a floating-gate transistor based analog implementation of adaptive filters that adapt based on the least-mean-square (LMS) learning algorithm. Floating-gate transistors are used for both weight adaptation and non-volatile weight storage. A current-mode approach results in a compact, low-power synapse. Experimental results from a prototype chip with a matrix of 16times4 synapses along with supporting circuitry fabricated in a 0.35 mum CMOS process are provided to demonstrate adaptation.

We propose an analog VLSI approach to implementing the projection neural networks adapted for the support vector machine with radial-basis kernel functions, which are realized by a proposed floating-gate bump circuit with the adjustable width. Other proposed circuits include simple current mirrors and log-domain filters. Neither resistors nor amplifiers are employed. Therefore it is suitable for large-scale neural network implementations. We show the measurement results of the bump circuit and verify the resulting analog signal processing system on the transistor level by using a SPICE simulator. The same approach can also be applied to the support vector regression. With these analog signal processing techniques, a low-power adaptive analog system without any analog-to-digital convertor but with the capability of learning, classifying, and regressing becomes feasible.

We have designed an automation tool which converts Simulink models to a Spice netlist, which can then be automatically compiled to FPAA (Field Programmable Analog Array) targeting code and implemented on an FPAA. This will allow DSP and neuromorphic engineers to have a fast, low power analog solution, without having to gain the necessary expertise in circuit design.

This paper discusses a 256times256 computational imager capable of performing separable transforms. Unlike traditional imagers, this imager performs computation on-chip and in- pixel. The primary computation performed is a separable matrix transformation. Several developments were made since a previous matrix transform imager to expand functionality and resolution. New circuit design emphasized dynamic range, accuracy, and speed. This architecture includes a novel overlapping block scheme allowing 8times8 general separable 2-D convolutions as well as 16times16 block transforms.

Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. This paper presents rapid prototyping results of a bandpass filter as a sample analog circuit using our floating-gate based large-scale FPAA. A major source of parasitics introduced during the circuit mapping process is interconnect switches used for routing. Our goal is to obtain models of the mapped circuits that can be simulated using SPICE in order to observe the impact of interconnect parasitics on the relevant analog metrics. Our results indicate that the mapped analog circuits obtain desired responses even with interconnect parasitics, clearly demonstrating the practicality of our FPAA.

We present a viewpoint showing that analog signal processing approaches are becoming configurable and programmable like their digital counterparts, while retaining a huge computational efficiency, for a given power budget, compared to their digital counterparts. We present recent results in programmable and configurable analog signal processing describing the widespread potential of these approaches. We also discuss issues with configurable systems, including size, power, and computational tradeoffs, as well as address the computational efficiency of these approaches.

We present an on-chip system that enables programming floating gate arrays at a high speed. The main component allowing this speedup is a floating point current measuring ADC operating over 4 decades at 10bit accuracy or 7decades at 7 bit accuracy. The conversion time is around 200μs till around 30 pA of current. The gate and drain voltages are set by on-chip DACs. The digital words for the DAC are sent by an FPGA through an SPI interface. The controller for sequencing the operations as well as the look-up-table with characterization data are on the FPGA. Algorithms using either pulse-width modulation or drain voltage modulation can be implemented.

We analyze the dynamics of a logarithmic transimpedance amplifier that are not explainable from its small-signal model. The amplifier was used both to measure pixel currents in an imager as well as currents from a floating gate array for accurate programming. We explain the marked asymmetry between the up-going and down-going current steps intuitively using circuit concepts and then based on phase-plane analysis. This analysis also helps develop a method of reducing the huge delay to down-going current steps.

This paper describes a transimpedance amplifier using logarithmic compression of the input current for wide dynamic range current sensing applications. Measurements demonstrate operation over currents ranging from 200fA to 2μA with an average error of 0.8%. It is analytically shown that the power dissipation of the non-adaptive structure varies linearly with dynamic range. This amplifier alleviates this strong dependance on dynamic range and achieves low-power operation by adapting the bias current of the amplifier depending on input current thus burning an average power of 3.45μW per decade of current. Either SNR or bandwidth can be made to trade-off with the input current depending on application. If the bandwidth is limited to 5kHz, it achieves an average SNR of 65dB.

The ability to recalibrate a system is an important feature in allowing that system to maintain optimal performance even in the face of new demands placed on that system by environmental changes or even consumers' desires. The use of floating-gate (FG) transistors provides programmability to analog circuitry and, hence, the ability to recalibrate an analog system. If the FG transistors are programmed indirectly by using a second transistor to perform hot-electron injection, then an analog system can be recalibrated and reprogrammed without ever having to take the circuit out of operation. In this paper, we present a technique for adjusting circuit properties while still in operation as well as example circuits in which this run-time programming is conducted.

We present a first-order model for pFET hotelectron injection that is consistent for subthreshold and above threshold current levels. Injection is a critical phenomena for high-precision programming of floating-gate devices, and accurate modeling fuels continued improvement of programming techniques. Previous work has shown good modeling for subthreshold operation; in this work we extend the modeling throughout the region, enabling improved programming algorithms for floating-gate switch elements, resistors, and highperformance circuit elements. We discuss the implementation of this model in CADENCE's version of SPICE.

Recently the authors presented transistor channel models of biological channels and the resulting implementation towards building spiking nodes, synapses, and dendrites. The authors also discussed how to build reconfigurable dendrites using programmable analog techniques. With all of this technology components available, the authors begin to address the question of the computation model possible using a dendrite element, as well as a network of dendrite elements. The authors discuss the connection between a dendrite element and a hidden Markov model (HMM) classifier branch, as well as a network of dendrites and somas to create an HMM classifier typical of what is used in speech recognition systems. The authors present simulation and experimental results for the branch elements; the authors also present initial results for a small dendrite based classifier structure to show the similarities to the HMM paradigm.

We focus on investigating large-scale FPAA topologies capable of high-frequency routing by building structures to avoid speed limitations of the routing fabric, while carefully considering the consumed power constraints. We approach this problem by building a special FPAA IC based on Transconductance Amplifiers to investigate the potential speed improvements over existing large-scale FPAA techniques with similar amplifier designs. This approach uses multiple levels of OTA based routing and computation to demonstrate the potential of these approaches combined with more traditional switch matrices. We present experimental results from an IC of 200 OTA devices fabricated in a 0.35μm CMOS process available through MOSIS. Initial experimental results show a range of working filter topologies which can operate with corner frequencies up to 15 MHz.

An analog sinusoidal oscillator usually involves some form of amplitude-limiting mechanism. We examine OTA nonlinearity as a choice for amplitude limiting, and introduce a general method for its use in OTA-C oscillators. We illustrate our discussion with an example design that we fabricated and tested. Our results show that OTA nonlinearity yields low-distortion oscillators at practically no power- or area cost

In this paper, we propose a novel bandpass filter design that incorporates automatic gain control (AGC). The gain control in the filter reduces the performance requirements of a wide-band AGC, and allows for low-power multichannel compression. The filter achieves up to15dB of compression on a65dB input dynamic range and is tunable over the audio frequency range, withμW power consumption and< 5%harmonic distortion.

We have developed a field programmable analog array (FPAA) that can be configured to synthesis and analyze a vast variety of circuits. This FPAA is a valuable platform for studying nonlinear dynamics in circuits, as it offers close to the flexibility of computer simulation, but with actual experimental results. We present data from a current mirror, a peak detector, and a second-order section

We present an implementation of a reconfigurable16-tapfinite impulse response filter for post-processing applications. This filter exploits the distributed arithmetic technique for signal processing and floating-gate voltage references for setting tunable analog coefficients. The filter is fabricated in0.5μmCMOS process, and its order can be increased at the cost of0.011mm2of die area and0.02mWof power per tap. Measurement results for low-pass and band-pass filters at50kHzsampling frequency are presented.

A procedure for synthesizing multiple-input translinear element (MITE) networks that implement a given system of translinear-loop equations (STLE) is presented. The minimum number of MITEs required for implementing the STLE, which is equal to the number of current variables in the STLE, is attained. The number of input gates of the MITEs is minimal amongst those MITE networks that satisfy the STLE and have the minimum number of MITEs. The synthesized MITE networks have a unique operating point and, in many cases, the network is guaranteed to be stable in a particular sense. This synthesis procedure exploits the relationship between MITE product-of-power-law (POPL) networks and linear diophantine equations which is explored in detail here.

In most reconfigurable systems, such as FPAAs and FPGAs, the switch element and its associated memory cell is a necessary overhead for performing computation with the active components. However, floating gate based switches in large-scale FPAAs can be programmed anywhere between simple "off" and "on" connections, which allows these programmable conductances to be used as computational elements within synthesized circuits. This decreases the notion of switches as computational dead weight and increases the potential computational area efficiency within FPAAs

Floating gate transistors make excellent switches for large-scale field-programmable analog arrays (FPAAs). In addition to simple "on" and "off" connections, they can be used as computational elements within synthesized circuits. However, the programmable range of these computational elements as well as the quality of an "on" switch can be limited by the particular switch topology and programming methods. To extend the useful range of floating gate switches, programming method improvements and indirectly programmed topologies are explored and demonstrated

Analog circuits and systems research and education can significantly benefit from the computational flexibility provided by large-scale FPAAs. The component density of these devices is sufficient to synthesize large systems in a short period of time. However, this level of reconfigurable and programmable complexity requires a development platform and CAD tools to demonstrate the capabilities of large-scale FPAAs before they can be widely accepted. To address this need, a self-contained FPAA setup has been developed along with an integrated software design flow. With only an Ethernet connection and an AC power outlet, a researcher or student can explore the numerous analog circuit possibilities provided by large-scale FPAAs.

Given a particular digital logic path and a desired operating frequency there exists an optimal trade off of dynamic, static, and short-circuit power dissipation. Techniques like DVS and variable thresholds exist to bring paths closer to this optimum, but intrinsic complications limit how close they can get. We present capacitively-biased, floating-gate CMOS (FG-CMOS) as a new, and intrinsically more efficient, logic family that removes many of these complications as well as giving rise to new dimensions of design and run time optimizations previously unattainable. Simulations are performed to explore the energy per cycle versus cycle time of arbitrary digital logic paths, and show FG-CMOS capable of running atleast 12% faster at the same power, or at 36% less power at the same speed, or when 20% slack is introduced 65% less power than regular CMOS or 37% less power than DVS CMOS. Devices were fabricated to show functionality, explore area ramifications, and to validate simulation.

A compact analog programmable multi-dimensional radial basis function (RBF) based classifier is demonstrated. The probability distribution of each feature in the templates modeled by a Gaussian function is approximately realized by the transfer characteristics of a floating-gate bump circuit. The maximum likelihood, the mean, and the variance can be inde- pendently programmed. By cascading these floating-gate bump circuits, the transfer characteristics approximate a multivariate Gaussian function with a diagonal covariance matrix. An array of these circuits constitute a compact multi-dimensional RBF- based classifier. When followed by a winner-take-all circuit, the RBF-based classifier forms an analog vector quantizer. We use receiver operating characteristic curves and equal error rate to evaluate the performance of our analog classifiers. We show that the analog classifier performance is comparable to that of digital counterparts. The proposed approach can be at least two orders of magnitude more power efficient than the digital microprocessors at the same task.

Estimating the direction of a diffusive source is a difficult problem, and little has been tried to estimate a chemical source subject to turbulence. Turbulence must be addressed if chemical localizer systems are to be effective. We look at how to quantify turbulence and develop a measure to locate a source in two different types of turbulence, modulated and unmodulated plumes. We show that a plume can be modeled linearly on a small-scale and that a wind measure for a stationary sensor array can indicate the direction of a chemical source with reasonable accuracy and time. This measure can be easily implemented in low-power computational electronics and applied to the detection of chemical leaks and illegal substances

A pre-charge buffer is designed in a 0.5 /spl mu/m CMOS process. The buffer has rail to rail input capability, and makes use of a slew boosting mechanism, which senses current to enhance slew rate. Sensing current avoids overshoots when the buffer exits the slew-mode. The buffer has less than 60 ns settling time with better than 2 % settling accuracy. The slew rate is 156 V//spl mu/s with a quiescent current of 265 /spl mu/A.

An analog circuit capable of accurately emulating large complex cells, or multiple less complex ones is described. This circuit is termed the FPNA or the field programmable neural array. It is analogous to the more familiar FPGA, but is composed of biologically relevant circuit components including active channels, dendrites, and synapses. Taking each of these circuit models, and adding a routing structure capable of routing outputs from cells (or external inputs) to any individual synapse at any node yields a device which is capable of emulating complex biological circuits. This circuit opens doors to investigating what particular types of computation individual cells are performing, as well as small networks simpler cells

This work details CMOS, bio-inspired circuits that are used to link an artificial neuron and a living neuron and between two living neurons. We read an intracellular signal from a living neuron, use an integrate-and-fire neuron as a simple processing element to detect the spikes, and an artificial synapse to send outputs to a living neuron. The key structure is an electronic synapse which is based around a floating-gate pFET. The charge on the floating-gate is analogous to the synaptic weight and can be modified. This modification can be viewed as similar to LTP and LTD. Since programming technology has greatly improved, these weights can be set quickly and accurately

This paper describes an implementation of a tunable CMOS resistor that can be fully integrated in a standard CMOS technology with low-power and low-voltage applications. It is built by exploiting the capacitive coupling and voltage storage capabilities of a floating-gate transistor. Also, a scaled-gate linearization technique is utilized to suppress the transistor nonlinearities in the triode region. The resistance of the proposed circuit is tuned by utilizing Fowler-Nordheim tunnelling and hot-electron injection quantum mechanical phenomena. We present experimental data from the chip that was fabricated in 0.5mum CMOS process, and show that this resistor exhibits total harmonic distortion (THD) better than 7-bit linearity for 1KHz 1Vppsinusoidal input

This paper describes an implementation of a low-voltage CMOS buffer employing a negative feedback to improve its performance. Floating-gate transistors are incorporated to obtain low-threshold transistors and to increase the input/output voltage swing of the circuit operating at 1.2V. The designed circuit is fabricated in 0.5mum CMOS process, and occupies 0.0214mm2. It achieves total harmonic distortion (THD) of 48dB for 10kHz 0.6Vppsinusoidal input signal

This paper describes a high signal-to-noise ratio capacitive sensing transducer with high power efficiency and high area efficiency. The circuit is an example of capacitive circuit and is based on a capacitive feedback charge amplifier. 78.6dB SNR in audio band is achieved with less than 0.5 /spl mu/W power consumption by making use of a floating-gate transistor. This design gives us the flexibility of controlling the charge on the floating node. The microphone sensor is interfaced with the amplifier to measure the performance of the transducer.

A new central pattern generator chip with 24 silicon neurons and reprogrammable connectivity is presented. The 3mm /spl times/ 3mm chip fabricated in a 3M2P 0.5/spl mu/m process contains 1032 synapses, each with multiple floating gates for storing parameters governing synaptic strength and polarity. Every neuron includes a dendritic compartment with 12 externally-addressable synaptic inputs and 24 recurrent synaptic inputs, enabling construction of a fully-interconnected network with sensory feedback from off-chip elements. In addition to describing the chip architecture and neuron circuits, preliminary results from single oscillating neurons and pairs of phase-locked neurons are shown. This work represents the realization of a design presented at ISCAS'05, and an improvement over our 2nd generation CPG chip presented at ISCAS'04.

We propose an image processing system using an analog transform imager chip. The transform imager is a CMOS imager which is capable of block transforms using floating-gates. Because the transform imager is highly programmable, it can perform various block transforms such as the Walsh-Hadamard transform, discrete sine transform (DST), and discrete cosine transform (DCT). We investigate the reduction of computations and power by a baseline JPEG compression system as an application. The 48/spl times/40 transform imager provides 144 MOPS/s using an area of 1.03 mm/sup 2/ in 0.5 /spl mu/m CMOS technology, and it has a much higher fill factor, 46%, compared with other focal plane imagers. The measured transformed images and the reconstructed images are presented to demonstrate the operations.

Summary form only given. Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality, flexibility, and usefulness. We explore the use of floating-gate devices as the core programmable element in a large-scale FPAA with applications in signal processing emphasized. An FPAA architecture is presented that offers increased functionality and flexibility in realizing analog signal processing systems, and experimental data from a testbed FPAA is shown. In addition, mainstream signal processing systems are discussed that can be effectively implemented on large-scale reconfigurable analog devices thereby realizing dramatic savings in power over traditional digital solutions and improved time-to-market over traditional analog designs.

We introduce the concept of cooperative analog-digital signal processing, and its implications on real-time signal processing functions. We discuss some of the trade-offs between performing operations in the analog computing circuit and digital computing circuits, and a general framework for “cooperative analog/digital signal processing systems” is presented. A key aspect of the cooperative analog/digital signal processing systems is the fact that new advances in analog VLSI circuits make it possible to developed advanced analog signal processing systems with programmable elements.

The Analog Speech Recognition project combines low-power analog signal processing and digital signal processing theory to provide low-power and robust speech processing systems. This project looks to bring together multiple analog signal processing (ASP) blocks into one large ASP system. These component blocks include an analog cepstrum. vector quantizer, and analog HMM. Finally. there are power dissipation comparisons made between the analog and digital systems based on the computations performed.

In this paper, we propose a continuous-time audio noise suppression algorithm for reducing stationary background noise in a single microphone signal. The algorithm is targeted for implementation in sub-threshold analog floating-gate transistor circuits for extremely low-power systems. The noise suppression algorithm divides the noisy signal into exponentially spaced sub-bands and estimates the noisy signal envelope and the noise envelope to calculate a time-varying gain for each sub-band based on each band's a posteriori SNR. A sigmoidal gain function in for use in the analog system is introduced and a normalized SNR is also proposed for consistent noise suppression for different input noise variances. Simulations of the system show promising results.

Nonlinear antennas combine advances in nonlinear dynamics, active antenna design, and analog microelectronics to generate beam steering and beam forming across an array of nonlinear oscillators. Nonlinear antennas exploit two phenomena typically shunned in traditional designs: nonlinear unit cells and interelement coupling. The design stems from nonlinear coupled differential equation analysis that by virtue of the dynamic control is far less complex than the linear counterparts by eliminating the need for phase shifters and beam forming computers. These advantages arise from incorporating nonlinear dynamics rather than limiting the system to linear quasisteady state operation. A theoretical framework describing beam shaping and beam forming by exploiting the phase, amplitude, and coupling dynamics of nonlinear oscillator arrays is presented. Experimental demonstration of nonlinear beam steering is realized using analog microelectronics.

The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off chip. Moving parameter storage on chip could save pins and allow us to create complex programmable analog systems. In this paper, we present a design for an on-chip non-volatile analog memory cell that can be configured in addressable arrays and programmed easily. We use floating-gate MOS transistors to store charge, and we use the processes of tunneling and pFET hot-electron injection to program values. With these designs, we achieve greater than 13-bit output precision with a 39 dB power supply rejection ratio and no crosstalk between memory cells.

We present a programmable continuous-time floating-gate Fourier processor that decomposes the frequency bands using analog bandpass filters, multiplies each channel by a non-volatile weight, and then recombines the frequency channels. A DSP would take a similar approach of computing a FFT, multiplying the frequency components by a weight, then computing an inverse FFT. We decompose the frequency bands of an incoming signal using the transistor only circuit model of the Autozeroing Floating-Gate Amplifier (AFGA) or also termed C4 (Capacitivly Coupled Current Conveyer). Each band decomposition is then fed through a floating gate multiplier to perform the band weighting. Finally, the multiplier outputs are summed using KCL to give a band weighted output of the original signal. We examine many options to reduce 2nd order harmonic problems inherent in the single sided C4. We present a method for programming arrays of floating gate devices that are used in the weighting of the bands. All of these pieces fit together to form an elegant and systematic Fourier processor.

We present a novel architecture for detecting spatiotemporal synchrony among pulse trains. This is useful for performing meaningful computation in a system where analog information is conveyed via the precise timing of spikes in addition to the mean spike rate-without explicitly leaving the spike domain. Using a resistive network to restrict the spatial extent of the window of meaningful synchrony, and an array of pseudo-AFGAs to restrict the temporal extent of the window, we are able to perform the synchrony detection task in continous time, without sampling. We have implemented this architecture using only 10 transistors per spatial channel, and have fabricated three 32-node linear arrays using a 1.2 /spl mu/ CMOS process. We present experimental results.

We describe the design, fabrication, characterization, and modeling of an array of single transistor synapses. The single transistor synapses simultaneously perform long term weight storage, compute the product of the input and floating gate value, and update the weight value according to a hebbian or a backpropagation learning rule. The charge on the floating gate is decreased by hot electron injection with high selectivity for a particular synapse. The charge on the floating gate is increased by electron tunneling, which results in high selectivity between rows, but much lower selectivity between columns along a row. When the steady state source current is used as the representation of the weight value, both the incrementing and decrementing functions are proportional to a power of the source current.

We describe single-transistor silicon synapses that compute, learn, and provide non-volatile memory retention. The single transistor synapses simultaneously perform long term weight storage, com(cid:173) pute the product of the input and the weight value, and update the weight value according to a Hebbian or a backpropagation learning rule. Memory is accomplished via charge storage on polysilicon floating gates, providing long-term retention without refresh. The synapses efficiently use the physics of silicon to perform weight up(cid:173) dates; the weight value is increased using tunneling and the weight value decreases using hot electron injection. The small size and low power operation of single transistor synapses allows the devel(cid:173) opment of dense synaptic arrays. We describe the design, fabri(cid:173) cation, characterization, and modeling of an array of single tran(cid:173) sistor synapses. When the steady state source current is used as the representation of the weight value, both the incrementing and decrementing functions are proportional to a power of the source current. The synaptic array was fabricated in the standard 21'm double - poly, analog process available from MOSIS.

We present a silicon model of an axon which shows promise as a building block for pulse-based neural computations involving cor(cid:173) relations of pulses across both space and time. The circuit shares a number of features with its biological counterpart including an excitation threshold, a brief refractory period after pulse comple(cid:173) tion, pulse amplitude restoration, and pulse width restoration. We provide a simple explanation of circuit operation and present data from a chip fabricated in a standard 2Jlm CMOS process through the MOS Implementation Service (MOSIS). We emphasize the ne(cid:173) cessity of the restoration of the width of the pulse in time for stable propagation in axons.