A detailed survey on the motivations, design, applications, current status, and limitations of computers designed for symbolic processing is provided. Symbolic processing computations are performed at the word, relation, or meaning levels, and the knowledge used in symbolic applications may be fuzzy, uncertain, indeterminate, and ill represented. Various techniques for knowledge representation and processing are discussed from both the designers' and users' points of view. The design and choice of a suitable language for symbolic processing and the mapping of applications into a software architecture are then considered. The process of refining the application requirements into hardware and software architectures is treated, and state-of-art sequential and parallel computers designed for symbolic processing are discussed.>

Provides a framework for approaching the learning of heuristic functions for numeric optimization problem solutions. The outline of a system called 'Techniques using Experimentation for Acquisition and Creation of HeuRistics 2.0' (TEACHER 2.0), for learning heuristic functions is presented. The system is unique in that it combines many learning techniques into one coherent system. It can be a powerful learning system as it allows the generation of heuristics based on an amalgamation of learning techniques and strategies. The value of the system is illustrated by an example in which TEACHER 2.0 learns a new heuristic that is superior to the typical heuristic for that problem domain.>

An approach to the design of reconfigurable tree architectures is presented in which spare processors are allocated at the leaves. The approach is unique in that spares are associated with subtrees and sharing of spares between these subtrees can occur. The Subtree Oriented Fault Tolerance (SOFT) approach is more reliable than previous approaches capable of tolerating link and switch failures for both single-chip and multichip tree implementations while reducing redundancy in terms of both spare processors and links. VLSI layout is O(n) for binary trees and is directly extensible to N-ary trees and fault tolerance through performance degradation.