Wolfgang Meyer 0002

Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data.

VLDB 2026 Research / reviewers in the wild / expert

dblp:34/34-2 · DBLP profile ↗

← Back

7ranked-venue papers

3as first author

0since 2021 · last 1998

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 7 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

4 papers

Electronic design automation · 86% Embedded and real-time systems · 11% Integrated circuit design · 3%

Topics — the 10 heaviest of 11, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Electronic design automation logic synthesis	2	1998	Partitioning and Optimizing Controllers Synthesized from Hierarchical High-Level Descriptions · DAC 1998 Design and Synthesis of Array Structured Telecommunication Processing Applications · DAC 1997
Electronic design automation › hardware verification and test fault simulation	2	1995	Active timing multilevel fault-simulation with switch-level accuracy · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995 Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy · DAC 1993
Electronic design automation hardware verification and test	2	1995	Active timing multilevel fault-simulation with switch-level accuracy · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995 Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy · DAC 1993
Electronic design automation › hardware verification and test › fault simulation hierarchical fault simulation	2	1995	Active timing multilevel fault-simulation with switch-level accuracy · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995 Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy · DAC 1993
Embedded and real-time systems › control systems controller synthesis	1	1998	Partitioning and Optimizing Controllers Synthesized from Hierarchical High-Level Descriptions · DAC 1998
Electronic design automation › high-level synthesis › register-transfer level synthesis control logic synthesis	1	1997	Design and Synthesis of Array Structured Telecommunication Processing Applications · DAC 1997
Electronic design automation high-level synthesis	1	1997	Design and Synthesis of Array Structured Telecommunication Processing Applications · DAC 1997
Electronic design automation › hardware verification and test › fault simulation switch-level fault simulation	1	1995	Active timing multilevel fault-simulation with switch-level accuracy · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995
Electronic design automation › hardware verification and test › fault modeling bridging fault	1	1995	Active timing multilevel fault-simulation with switch-level accuracy · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995
Electronic design automation › circuit modeling switch-level modeling	1	1993	Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy · DAC 1993

Methods — techniques the papers use, named apart from their topics

structured control logic design · 0.0array frames · 0.0single fault propagation · 0.0inertial delay model · 0.0switch-level fault models · 0.0hierarchical multi-level fault simulation · 0.0

Year	Publication	Venue	Position
1998	Partitioning and Optimizing Controllers Synthesized from Hierarchical High-Level Descriptions abstract Abstract- This paper describes methods for partitioning and optimizing controllers described by hierarchical high-level descriptions. The methods utilize the structure of the high-level description, provide flexible exploration of the trade-off between combinational logic and registers to reduce implementation cost, and allow the designer to control the synthesis process. Results are presented using industrial examples. 1. Andrew Seawright, Wolfgang Meyer 0002	DAC	2
1997	Design and Synthesis of Array Structured Telecommunication Processing Applications abstract This paper describes an automated design andsynthesis methodology for telecommunications ASIC's.Array frames, an array structured visualization of theprocessing problem, are used in the specification anddebugging of the design. This allows design much closer to thespecification level. The array frame concept is integratedinto the Dali structured control logic design environment. AnSDH (Synchronous Digital Hierarchy) style exampledemon-strates the use of array frames. The array frame approachwas successfully applied in industrial applications. Wolfgang Meyer 0002, Andrew Seawright, Fumiya Tada	DAC	1
1995	Active timing multilevel fault-simulation with switch-level accuracy abstract This paper describes SATISFAULT, a new hierarchical multilevel fault simulator with switch-level fault models and switch-level accuracy. SATISFAULT's intelligent scheduling mechanism switches between the abstraction levels to force simulation at the highest, thus fastest, possible level of abstraction without losing switch-level accuracy. The simulation algorithm is based on single fault-propagation for active faults. It deals with multiple abstraction levels and supports the inertial delay model. As a result, even large circuits may be fault-simulated accurately with all faults injected at the switch-level. Complete fault-simulation of all transistors stuck-on and stuck-open of circuits up to 105000 transistors including faults inside flip-flops is possible in reasonable time. In addition, SATISFAULT is also capable of simulating bridging faults for IddQ detectability.> Wolfgang Meyer 0002, Raúl Camposano	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1
1993	Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy abstract This paper presents FEHSIM, a new hierarchical multi-level fault simulator with switch-level fault models and swttch-level accuracy. Wolfgang Meyer 0002, Raúl Camposano	DAC	1
1993	CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects abstract Beyond the static stuck-at fault model, delay fault testing and static overcurrent testing have been suggested as approaches yielding reasonable fault coverage in CMOS circuits. Based on detailed simulations of resistive stuck-on-, stuck-open-, and bridging faults for typical CMOS circuits, this paper presents an analysis of their detectability and requirements for current and timing resolutions in overcurrent and delay fault testing.> Heinrich Theodor Vierhaus, Wolfgang Meyer 0002, Uwe Gläser	ITC	2
1993	Fault behavior and testability of asynchronous CMOS circuits Heinrich Theodor Vierhaus, Wolfgang Meyer 0002, Uwe Gläser, Raúl Camposano	Microprocess. Microprogramming	2
1992	CMOS transistor faults and bridging faults: Testability by delay effects and overcurrents Uwe Hübner, Wolfgang Meyer 0002, Heinrich Theodor Vierhaus	Microprocess. Microprogramming	2